From: Stefan Agner stefan.agner@toradex.com
For i.MX 6SoloX/i.MX 7 simple binary files are used to boot the auxiliary CPU core (Cortex-M4). This patch moves the "parsing" of this binary firmwares to the SoC independent code. This allows to add different binary formats more easily.
While at it, also move the comment about the inner workings how to boot the Cortex-M4 core to a more appropriate location.
Signed-off-by: Stefan Agner stefan.agner@toradex.com ---
arch/arm/cpu/armv7/mx6/soc.c | 18 ++++++++++-------- arch/arm/cpu/armv7/mx7/soc.c | 19 +++++++++++-------- arch/arm/imx-common/imx_bootaux.c | 21 +++++++++------------ 3 files changed, 30 insertions(+), 28 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index dd94797514..642195b97c 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -666,16 +666,18 @@ void imx_setup_hdmi(void) #endif
#ifdef CONFIG_IMX_BOOTAUX -int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) +/* + * Per the cortex-M reference manual, the reset vector of M4 needs + * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses + * of that vector. So to boot M4, the A core must build the M4's reset + * vector with getting the PC and SP from image and filling them to + * TCMUL. When M4 is kicked, it will load the PC and SP by itself. + * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for + * accessing the M4 TCMUL. + */ +int arch_auxiliary_core_up(u32 core_id, u32 stack, u32 pc) { struct src *src_reg; - u32 stack, pc; - - if (!boot_private_data) - return -EINVAL; - - stack = *(u32 *)boot_private_data; - pc = *(u32 *)(boot_private_data + 4);
/* Set the stack and pc to M4 bootROM */ writel(stack, M4_BOOTROM_BASE_ADDR); diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index 8422f24573..e949b8e557 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -311,17 +311,20 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) #endif
#ifdef CONFIG_IMX_BOOTAUX -int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) + +/* + * Per the cortex-M reference manual, the reset vector of M4 needs + * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses + * of that vector. So to boot M4, the A core must build the M4's reset + * vector with getting the PC and SP from image and filling them to + * TCMUL. When M4 is kicked, it will load the PC and SP by itself. + * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for + * accessing the M4 TCMUL. + */ +int arch_auxiliary_core_up(u32 core_id, u32 stack, u32 pc) { - u32 stack, pc; struct src *src_reg = (struct src *)SRC_BASE_ADDR;
- if (!boot_private_data) - return 1; - - stack = *(u32 *)boot_private_data; - pc = *(u32 *)(boot_private_data + 4); - /* Set the stack and pc to M4 bootROM */ writel(stack, M4_BOOTROM_BASE_ADDR); writel(pc, M4_BOOTROM_BASE_ADDR + 4); diff --git a/arch/arm/imx-common/imx_bootaux.c b/arch/arm/imx-common/imx_bootaux.c index 69026df763..4d697b0660 100644 --- a/arch/arm/imx-common/imx_bootaux.c +++ b/arch/arm/imx-common/imx_bootaux.c @@ -8,13 +8,13 @@ #include <command.h>
/* Allow for arch specific config before we boot */ -static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) +static int __arch_auxiliary_core_up(u32 core_id, u32 stack, u32 pc) { /* please define platform specific arch_auxiliary_core_up() */ return CMD_RET_FAILURE; }
-int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data) +int arch_auxiliary_core_up(u32 core_id, u32 stack, u32 pc) __attribute__((weak, alias("__arch_auxiliary_core_up")));
/* Allow for arch specific config before we boot */ @@ -31,17 +31,10 @@ int arch_auxiliary_core_check_up(u32 core_id) * To i.MX6SX and i.MX7D, the image supported by bootaux needs * the reset vector at the head for the image, with SP and PC * as the first two words. - * - * Per the cortex-M reference manual, the reset vector of M4 needs - * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses - * of that vector. So to boot M4, the A core must build the M4's reset - * vector with getting the PC and SP from image and filling them to - * TCMUL. When M4 is kicked, it will load the PC and SP by itself. - * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for - * accessing the M4 TCMUL. */ int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + u32 stack, pc; ulong addr; int ret, up;
@@ -56,9 +49,13 @@ int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
addr = simple_strtoul(argv[1], NULL, 16);
- printf("## Starting auxiliary core at 0x%08lX ...\n", addr); + /* Assume binary file with vector table at the beginning */ + stack = *(u32 *)addr; + pc = *(u32 *)(addr + 4); + + printf("## Starting auxiliary core at 0x%08X ...\n", pc);
- ret = arch_auxiliary_core_up(0, addr); + ret = arch_auxiliary_core_up(0, stack, pc); if (ret) return CMD_RET_FAILURE;