This commit moves the FPGA descriptor definition to mach-zynq, where it makes more sense.
Based on patches from Ariel D'Alessandro ariel@vanguardiasur.com.ar, and Ezequiel Garcia ezequiel@vanguardiasur.com.ar
Signed-off-by: Michal Simek michal.simek@xilinx.com ---
It is just test how this can be done. Didn't spent enought time to prepare it to the state that it is fine to merge it. ARCH_EARLY_INIT_R, ifdefs in zynqpl.h and cpu_desc_id are questionable. I didn't even test it on HW. Especially cse target needs to be properly checked.
--- arch/arm/Kconfig | 1 + arch/arm/mach-zynq/cpu.c | 62 +++++++++++++++++++++++++++- board/xilinx/zynq/board.c | 63 ----------------------------- configs/zynq_cse_qspi_defconfig | 1 + include/zynqpl.h | 89 ++++++++++++++++------------------------- 5 files changed, 97 insertions(+), 119 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a423aa96296c..c542d1beacb9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -819,6 +819,7 @@ config ARCH_ZYNQ imply CMD_CLK imply FAT_WRITE imply CMD_SPL + imply ARCH_EARLY_INIT_R
config ARCH_ZYNQMP bool "Xilinx ZynqMP based platform" diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index ee1c1a943b66..b544050adcfd 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -5,14 +5,41 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <zynqpl.h> #include <asm/io.h> #include <asm/arch/clk.h> -#include <asm/arch/sys_proto.h> #include <asm/arch/hardware.h> +#include <asm/arch/ps7_init_gpl.h> +#include <asm/arch/sys_proto.h>
#define ZYNQ_SILICON_VER_MASK 0xF0000000 #define ZYNQ_SILICON_VER_SHIFT 28
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) +xilinx_desc fpga = { .family = xilinx_zynq, .iface = devcfg, .operations = &zynq_op, }; +#endif + +static const struct { + u8 idcode; +#if defined(CONFIG_FPGA) + u32 fpga_size; +#endif + char *devicename; +} zynq_fpga_descs[] = { + ZYNQ_DESC(7Z007S), + ZYNQ_DESC(7Z010), + ZYNQ_DESC(7Z012S), + ZYNQ_DESC(7Z014S), + ZYNQ_DESC(7Z015), + ZYNQ_DESC(7Z020), + ZYNQ_DESC(7Z030), + ZYNQ_DESC(7Z035), + ZYNQ_DESC(7Z045), + ZYNQ_DESC(7Z100), + { /* Sentinel */ }, +}; + int arch_cpu_init(void) { zynq_slcr_unlock(); @@ -60,3 +87,36 @@ void enable_caches(void) dcache_enable(); } #endif + +static int __maybe_unused cpu_desc_id(void) +{ + u32 idcode; + u8 i; + + idcode = zynq_slcr_get_idcode(); + for (i = 0; zynq_fpga_descs[i].idcode; i++) { + if (zynq_fpga_descs[i].idcode == idcode) + return i; + } + + return 0; +} + +#if defined(CONFIG_ARCH_EARLY_INIT_R) +int arch_early_init_r(void) +{ +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) + int cpu_id = cpu_desc_id(); + + if (cpu_id < 0) + return 0; + + fpga.size = zynq_fpga_descs[cpu_id].fpga_size; + fpga.name = zynq_fpga_descs[cpu_id].devicename; + fpga_init(); + fpga_add(fpga_xilinx, &fpga); +#endif + return 0; +} +#endif diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index e59038106aa6..837d300c691e 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -15,71 +15,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) -static xilinx_desc fpga; - -/* It can be done differently */ -static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7); -static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); -static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12); -static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14); -static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); -static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); -static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); -static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35); -static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); -static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); -#endif - int board_init(void) { -#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) - u32 idcode; - - idcode = zynq_slcr_get_idcode(); - - switch (idcode) { - case XILINX_ZYNQ_7007S: - fpga = fpga007s; - break; - case XILINX_ZYNQ_7010: - fpga = fpga010; - break; - case XILINX_ZYNQ_7012S: - fpga = fpga012s; - break; - case XILINX_ZYNQ_7014S: - fpga = fpga014s; - break; - case XILINX_ZYNQ_7015: - fpga = fpga015; - break; - case XILINX_ZYNQ_7020: - fpga = fpga020; - break; - case XILINX_ZYNQ_7030: - fpga = fpga030; - break; - case XILINX_ZYNQ_7035: - fpga = fpga035; - break; - case XILINX_ZYNQ_7045: - fpga = fpga045; - break; - case XILINX_ZYNQ_7100: - fpga = fpga100; - break; - } -#endif - -#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) - fpga_init(); - fpga_add(fpga_xilinx, &fpga); -#endif - return 0; }
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 9659faefbf33..933a21f69f2f 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -9,6 +9,7 @@ CONFIG_DEBUG_UART=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTDELAY=-1 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_ARCH_EARLY_INIT_R is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/include/zynqpl.h b/include/zynqpl.h index 5a34a17daefe..9d3884c65c0f 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -12,23 +12,18 @@
#include <xilinx.h>
-#if defined(CONFIG_FPGA_ZYNQPL) extern struct xilinx_fpga_op zynq_op; -# define FPGA_ZYNQPL_OPS &zynq_op -#else -# define FPGA_ZYNQPL_OPS NULL -#endif
-#define XILINX_ZYNQ_7007S 0x3 -#define XILINX_ZYNQ_7010 0x2 -#define XILINX_ZYNQ_7012S 0x1c -#define XILINX_ZYNQ_7014S 0x8 -#define XILINX_ZYNQ_7015 0x1b -#define XILINX_ZYNQ_7020 0x7 -#define XILINX_ZYNQ_7030 0xc -#define XILINX_ZYNQ_7035 0x12 -#define XILINX_ZYNQ_7045 0x11 -#define XILINX_ZYNQ_7100 0x16 +#define XILINX_ZYNQ_XC7Z007S 0x3 +#define XILINX_ZYNQ_XC7Z010 0x2 +#define XILINX_ZYNQ_XC7Z012S 0x1c +#define XILINX_ZYNQ_XC7Z014S 0x8 +#define XILINX_ZYNQ_XC7Z015 0x1b +#define XILINX_ZYNQ_XC7Z020 0x7 +#define XILINX_ZYNQ_XC7Z030 0xc +#define XILINX_ZYNQ_XC7Z035 0x12 +#define XILINX_ZYNQ_XC7Z045 0x11 +#define XILINX_ZYNQ_XC7Z100 0x16
/* Device Image Sizes */ #define XILINX_XC7Z007S_SIZE 16669920/8 @@ -42,45 +37,29 @@ extern struct xilinx_fpga_op zynq_op; #define XILINX_XC7Z045_SIZE 106571232/8 #define XILINX_XC7Z100_SIZE 139330784/8
-/* Descriptor Macros */ -#define XILINX_XC7Z007S_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z007s" } - -#define XILINX_XC7Z010_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z010" } - -#define XILINX_XC7Z012S_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z012s" } - -#define XILINX_XC7Z014S_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z014s" } - -#define XILINX_XC7Z015_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z015" } - -#define XILINX_XC7Z020_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z020" } - -#define XILINX_XC7Z030_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z030" } - -#define XILINX_XC7Z035_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z035" } - -#define XILINX_XC7Z045_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z045" } - -#define XILINX_XC7Z100_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ - "7z100" } +/* Device Names */ +#define XILINX_XC7Z007S_NAME "7z007s" +#define XILINX_XC7Z010_NAME "7z010" +#define XILINX_XC7Z012S_NAME "7z012s" +#define XILINX_XC7Z014S_NAME "7z014s" +#define XILINX_XC7Z015_NAME "7z015" +#define XILINX_XC7Z020_NAME "7z020" +#define XILINX_XC7Z030_NAME "7z030" +#define XILINX_XC7Z035_NAME "7z035" +#define XILINX_XC7Z045_NAME "7z045" +#define XILINX_XC7Z100_NAME "7z100" + +#if defined(CONFIG_FPGA) +#define ZYNQ_DESC(name) { \ + .idcode = XILINX_ZYNQ_XC##name, \ + .fpga_size = XILINX_XC##name##_SIZE, \ + .devicename = XILINX_XC##name##_NAME \ + } +#else +#define ZYNQ_DESC(name) { \ + .idcode = XILINX_ZYNQ_XC##name, \ + .devicename = XILINX_XC##name##_NAME \ + } +#endif
#endif /* _ZYNQPL_H_ */