USB was broken initially. Power polarity should be direct.
Signed-off-by: Sergei Ianovich ynvich@gmail.com CC: Marek Vasut marex@denx.de --- Changes v1..v2 * new patch
board/icpdas/lp8x4x/lp8x4x.c | 22 +++++++++++++--------- include/configs/lp8x4x.h | 3 +-- 2 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/board/icpdas/lp8x4x/lp8x4x.c b/board/icpdas/lp8x4x/lp8x4x.c index 1b68ef3..0888960 100644 --- a/board/icpdas/lp8x4x/lp8x4x.c +++ b/board/icpdas/lp8x4x/lp8x4x.c @@ -60,15 +60,21 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_CMD_USB int usb_board_init(void) { - writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), - UHCHR); + writel(readl(CKEN) | CKEN10_USBHOST, CKEN); + + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); + udelay(11); + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
while (readl(UHCHR) & UHCHR_FSBIR) continue; /* required by checkpath.pl */
+ writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); + writel(readl(UHCRHDA) & ~(0x1000), UHCRHDA); + writel(readl(UHCRHDA) | 0x800, UHCRHDA); + writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
@@ -82,10 +88,6 @@ int usb_board_init(void) /* Set port power control mask bits, only 3 ports. */ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
- /* enable port 2 */ - writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | - UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); - return 0; }
@@ -94,7 +96,7 @@ void usb_board_init_fail(void) return; }
-void usb_board_stop(void) +int usb_board_stop(void) { writel(readl(UHCHR) | UHCHR_FHR, UHCHR); udelay(11); @@ -103,9 +105,11 @@ void usb_board_stop(void) writel(readl(UHCCOMS) | 1, UHCCOMS); udelay(10);
+ writel(readl(UHCHR) | UHCHR_SSEP0 | UHCHR_SSE, UHCHR); + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
- return; + return 0; } #endif
diff --git a/include/configs/lp8x4x.h b/include/configs/lp8x4x.h index 6df6f2b..2c03425 100644 --- a/include/configs/lp8x4x.h +++ b/include/configs/lp8x4x.h @@ -190,7 +190,7 @@ #define CONFIG_SYS_GAFR1_L_VAL 0x999a955a #define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x55f0a402 +#define CONFIG_SYS_GAFR2_U_VAL 0x55f9a402 #define CONFIG_SYS_GAFR3_L_VAL 0x540a950c #define CONFIG_SYS_GAFR3_U_VAL 0x00001599
@@ -238,7 +238,6 @@ */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_BOARD_INIT #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000