Enable new features and provide require device-tree config so that U-Boot produces the correct ACPI tables on Coral.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v4: - Correct DPTF enable property - Correct compatible string for gma device
Changes in v3: - Rebase to master
Changes in v2: - Rebase to master
Changes in v1: - Add NHLT information - Fix i2c PCI addresses - Rename acpi-probed to linux,probed - Rename cpi,hid-desc-reg-offset to hid-desc-addr - UIse hid-over-i2 compatible string - Update ACPI ordering to include multiple CPUs - Use acpi,ddn instead of acpi,desc
arch/x86/dts/chromebook_coral.dts | 226 +++++++++++++++++++++++++++-- configs/chromebook_coral_defconfig | 11 +- 2 files changed, 221 insertions(+), 16 deletions(-)
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index a17a9c28003..893a59b1620 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -15,14 +15,20 @@ #include "flashmap-16mb-rw.dtsi" #endif
+#include <dt-bindings/clock/intel-clock.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/x86-irq.h> +#include <asm/e820.h> #include <asm/intel_pinctrl_defs.h> #include <asm/arch-apollolake/cpu.h> +#include <asm/arch-apollolake/gpe.h> #include <asm/arch-apollolake/gpio.h> #include <asm/arch-apollolake/iomap.h> #include <asm/arch-apollolake/pm.h> #include <dt-bindings/clock/intel-clock.h> #include <asm/arch-apollolake/fsp/fsp_m_upd.h> #include <asm/arch-apollolake/fsp/fsp_s_upd.h> +#include <dt-bindings/sound/nhlt.h>
/ { model = "Google Coral"; @@ -40,6 +46,14 @@ i2c5 = &i2c_5; i2c6 = &i2c_6; i2c7 = &i2c_7; + mmc1 = &sdmmc; + }; + + board: board { + compatible = "google,coral"; + recovery-gpios = <&gpio_nw (-1) GPIO_ACTIVE_LOW>; + write-protect-gpios = <&gpio_nw GPIO_75 GPIO_ACTIVE_HIGH>; + phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>; };
config { @@ -48,6 +62,15 @@
chosen { stdout-path = &serial; + e820-entries = /bits/ 64 < + IOMAP_P2SB_BAR IOMAP_P2SB_SIZE E820_RESERVED + MCH_BASE_ADDRESS MCH_SIZE E820_RESERVED>; + u-boot,acpi-ssdt-order = <&cpu_0 &cpu_1 &cpu_2 &cpu_3 + &i2c_0 &i2c_1 &i2c_2 &i2c_3 &i2c_4 &i2c_5 + &sdmmc &maxim_codec &wifi &da_codec &tpm + &elan_touchscreen &raydium_touchscreen + &elan_touchpad &synaptics_touchpad &wacom_digitizer>; + u-boot,acpi-dsdt-order = <&board &lpc>; };
clk: clock { @@ -60,7 +83,7 @@ #address-cells = <1>; #size-cells = <0>;
- cpu@0 { + cpu_0: cpu@0 { u-boot,dm-pre-reloc; device_type = "cpu"; compatible = "intel,apl-cpu"; @@ -68,21 +91,21 @@ intel,apic-id = <0>; };
- cpu@1 { + cpu_1: cpu@1 { device_type = "cpu"; compatible = "intel,apl-cpu"; reg = <1>; intel,apic-id = <2>; };
- cpu@2 { + cpu_2: cpu@2 { device_type = "cpu"; compatible = "intel,apl-cpu"; reg = <2>; intel,apic-id = <4>; };
- cpu@3 { + cpu_3: cpu@3 { device_type = "cpu"; compatible = "intel,apl-cpu"; reg = <3>; @@ -128,6 +151,10 @@ */ fsp_s: fsp-s { }; + + nhlt { + intel,dmic-channels = <4>; + }; };
punit@0,1 { @@ -136,21 +163,29 @@ compatible = "intel,apl-punit"; };
+ gma@2,0 { + reg = <0x00001000 0 0 0 0>; + compatible = "fsp-fb"; + }; + p2sb: p2sb@d,0 { u-boot,dm-pre-reloc; reg = <0x02006810 0 0 0 0>; compatible = "intel,p2sb"; early-regs = <IOMAP_P2SB_BAR 0x100000>; + pci,no-autoconfig;
n { compatible = "intel,apl-pinctrl"; u-boot,dm-pre-reloc; intel,p2sb-port-id = <PID_GPIO_N>; + acpi,path = "\_SB.GPO0"; gpio_n: gpio-n { compatible = "intel,gpio"; u-boot,dm-pre-reloc; gpio-controller; #gpio-cells = <2>; + linux-name = "INT3452:00"; }; };
@@ -159,11 +194,13 @@ compatible = "intel,apl-pinctrl"; intel,p2sb-port-id = <PID_GPIO_NW>; #gpio-cells = <2>; + acpi,path = "\_SB.GPO1"; gpio_nw: gpio-nw { compatible = "intel,gpio"; u-boot,dm-pre-reloc; gpio-controller; #gpio-cells = <2>; + linux-name = "INT3452:01"; }; };
@@ -172,11 +209,13 @@ compatible = "intel,apl-pinctrl"; intel,p2sb-port-id = <PID_GPIO_W>; #gpio-cells = <2>; + acpi,path = "\_SB.GPO2"; gpio_w: gpio-w { compatible = "intel,gpio"; u-boot,dm-pre-reloc; gpio-controller; #gpio-cells = <2>; + linux-name = "INT3452:02"; }; };
@@ -185,11 +224,13 @@ compatible = "intel,apl-pinctrl"; intel,p2sb-port-id = <PID_GPIO_SW>; #gpio-cells = <2>; + acpi,path = "\_SB.GPO3"; gpio_sw: gpio-sw { compatible = "intel,gpio"; u-boot,dm-pre-reloc; gpio-controller; #gpio-cells = <2>; + linux-name = "INT3452:03"; }; };
@@ -238,6 +279,24 @@ gpe0-en = <0x30>; };
+ audio@e,0 { + reg = <0x7000 0 0 0 0>; + compatible = "simple-bus"; + acpi,name = "HDAS"; + i2s { + compatible = "fred"; + }; + maxim_codec: maxim-codec { + compatible = "maxim,max98357a"; + acpi,ddn = "Maxim Integrated 98357A Amplifier"; + sdmode-gpios = <&gpio_n GPIO_76 GPIO_ACTIVE_HIGH>; + sdmode-delay = <5>; + acpi,name = "MAXM"; + acpi,hid = "MX98357A"; + acpi,audio-link = <AUDIO_LINK_SSP5>; + }; + }; + spi: fast-spi@d,2 { u-boot,dm-pre-reloc; reg = <0x02006a10 0 0 0 0>; @@ -267,19 +326,63 @@ }; };
+ /* WiFi */ + pcie-a0@14,0 { + reg = <0x0000a000 0 0 0 0>; + acpi,name = "RP01"; + wifi: wifi { + compatible = "intel,generic-wifi"; + acpi,ddn = "Intel WiFi"; + acpi,name = "WF00"; + acpi,wake = <GPE0_DW3_00>; + interrupts-extended = <&acpi_gpe 0x3c 0>; + }; + }; + i2c_0: i2c2@16,0 { compatible = "intel,apl-i2c"; reg = <0x0200b010 0 0 0 0>; clocks = <&clk CLK_I2C>; i2c-scl-rising-time-ns = <104>; i2c-scl-falling-time-ns = <52>; + clock-frequency = <400000>; + i2c,speeds = <100000 400000 1000000>; + #address-cells = <1>; + #size-cells = <0>; + da_codec: da-codec { + reg = <0x1a>; + compatible = "dlg,da7219"; + interrupts-extended = <&acpi_gpe GPIO_116_IRQ + (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>; + acpi,name = "DLG7"; + acpi,ddn = "Dialog Semiconductor DA7219 Audio Codec"; + acpi,audio-link = <AUDIO_LINK_SSP1>; + dlg,micbias-lvl = <2600>; + dlg,mic-amp-in-sel = "diff"; + da7219_aad { + dlg,btn-cfg = <50>; + dlg,mic-det-thr = <500>; + dlg,jack-ins-deb = <20>; + dlg,jack-det-rate = "32ms_64ms"; + dlg,jack-rem-deb = <1>; + dlg,a-d-btn-thr = <0xa>; + dlg,d-b-btn-thr = <0x16>; + dlg,b-c-btn-thr = <0x21>; + dlg,c-mic-btn-thr = <0x3e>; + dlg,btn-avg = <4>; + dlg,adc-1bit-rpt = <1>; + }; + }; };
i2c_1: i2c2@16,1 { compatible = "intel,apl-i2c"; reg = <0x0200b110 0 0 0 0>; clocks = <&clk CLK_I2C>; - status = "disabled"; + clock-frequency = <400000>; + i2c,speeds = <100000 400000 1000000 3400000>; + i2c-scl-rising-time-ns = <52>; + i2c-scl-falling-time-ns = <52>; };
i2c_2: i2c2@16,2 { @@ -288,53 +391,130 @@ #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; + i2c,speeds = <100000 400000 1000000>; clocks = <&clk CLK_I2C>; i2c-scl-rising-time-ns = <57>; i2c-scl-falling-time-ns = <28>; - tpm@50 { + tpm: tpm@50 { reg = <0x50>; compatible = "google,cr50"; u-boot,i2c-offset-len = <0>; ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>; - interrupts-extended = <&acpi_gpe 0x3c 0>; + interrupts-extended = <&acpi_gpe GPIO_28_IRQ + IRQ_TYPE_EDGE_FALLING>; + acpi,hid = "GOOG0005"; + acpi,ddn = "I2C TPM"; + acpi,name = "TPMI"; }; };
i2c_3: i2c2@16,3 { compatible = "intel,apl-i2c"; - reg = <0x0200b110 0 0 0 0>; + reg = <0x0200b310 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&clk CLK_I2C>; i2c-scl-rising-time-ns = <76>; i2c-scl-falling-time-ns = <164>; + clock-frequency = <400000>; + i2c,speeds = <100000 400000>; + elan_touchscreen: elan-touchscreen@10 { + compatible = "i2c-chip"; + reg = <0x10>; + acpi,hid = "ELAN0001"; + acpi,ddn = "ELAN Touchscreen"; + interrupts-extended = <&acpi_gpe GPIO_21_IRQ + IRQ_TYPE_EDGE_FALLING>; + linux,probed; + reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>; + reset-delay-ms = <20>; + enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>; + enable-delay-ms = <1>; + acpi,has-power-resource; + }; + + raydium_touchscreen: raydium-touchscreen@39 { + compatible = "i2c-chip"; + reg = <0x39>; + acpi,hid = "RAYD0001"; + acpi,ddn = "Raydium Touchscreen"; + interrupts-extended = <&acpi_gpe GPIO_21_IRQ + IRQ_TYPE_EDGE_FALLING>; + linux,probed; + reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>; + reset-delay-ms = <1>; + enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>; + enable-delay-ms = <50>; + acpi,has-power-resource; + }; };
i2c_4: i2c2@17,0 { compatible = "intel,apl-i2c"; - reg = <0x0200b110 0 0 0 0>; + reg = <0x0200b810 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&clk CLK_I2C>; i2c-sda-hold-time-ns = <350>; i2c-scl-rising-time-ns = <114>; i2c-scl-falling-time-ns = <164>; + clock-frequency = <400000>; + i2c,speeds = <100000 400000>; + elan_touchpad: elan-touchpad@15 { + compatible = "i2c-chip"; + reg = <0x15>; + u-boot,i2c-offset-len = <0>; + acpi,hid = "ELAN0000"; + acpi,ddn = "ELAN Touchpad"; + interrupts-extended = <&acpi_gpe GPIO_18_IRQ + IRQ_TYPE_EDGE_FALLING>; + acpi,wake = <GPE0_DW1_15>; + linux,probed; + }; + synaptics_touchpad: synaptics-touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + acpi,hid = "PNP0C50"; + acpi,ddn = "Synaptics Touchpad"; + interrupts-extended = <&acpi_gpe GPIO_18_IRQ + IRQ_TYPE_EDGE_FALLING>; + acpi,wake = <GPE0_DW1_15>; + linux,probed; + hid-descr-addr = <0x20>; + }; };
i2c_5: i2c2@17,1 { compatible = "intel,apl-i2c"; - reg = <0x0200b110 0 0 0 0>; + reg = <0x0200b910 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&clk CLK_I2C>; i2c-scl-rising-time-ns = <76>; i2c-scl-falling-time-ns = <164>; + clock-frequency = <400000>; + i2c,speeds = <100000 400000 1000000>; + wacom_digitizer: wacom-digitizer@9 { + compatible = "hid-over-i2c"; + reg = <0x9>; + acpi,hid = "WCOM50C1"; + acpi,ddn = "WCOM Digitizer"; + interrupts-extended = <&acpi_gpe GPIO_13_IRQ + (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>; + hid-descr-addr = <0x1>; + }; };
i2c_6: i2c2@17,2 { compatible = "intel,apl-i2c"; - reg = <0x0200b110 0 0 0 0>; + reg = <0x0200ba10 0 0 0 0>; clocks = <&clk CLK_I2C>; status = "disabled"; };
i2c_7: i2c2@17,3 { compatible = "intel,apl-i2c"; - reg = <0x0200b110 0 0 0 0>; + reg = <0x0200bb10 0 0 0 0>; clocks = <&clk CLK_I2C>; status = "disabled"; }; @@ -347,6 +527,15 @@ reg-shift = <2>; clock-frequency = <1843200>; current-speed = <115200>; + acpi,name = "URT3"; + pci,no-autoconfig; + }; + + sdmmc: sdmmc@1b,0 { + reg = <0x0000d800 0 0 0 0>; + compatible = "intel,apl-sd"; + cd-gpios = <&gpio_n GPIO_177 GPIO_ACTIVE_LOW>; + acpi,name = "SDCD"; };
pch: pch@1f,0 { @@ -356,7 +545,7 @@ #address-cells = <1>; #size-cells = <1>;
- lpc { + lpc: lpc { compatible = "intel,apl-lpc"; #address-cells = <1>; #size-cells = <0>; @@ -594,12 +783,17 @@ * [6:0] steps of delay for HS200, each 125ps */ /* Enable DPTF */ - dptf-enable; + fsps,dptf-enabled; fsps,emmc-tx-data-cntl1 = <0x0c16>; fsps,emmc-tx-data-cntl2 = <0x28162828>; fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>; fsps,emmc-rx-cmd-data-cntl2 = <0x10008>;
+ /* Enable Audio Clock and Power gating */ + fsps,hd-audio-clk-gate = <1>; + fsps,hd-audio-pwr-gate = <1>; + fsps,bios-cfg-lock-down = <1>; + /* Enable WiFi */ fsps,pcie-root-port-en = [01 00 00 00 00 00]; fsps,pcie-rp-hot-plug = [00 00 00 00 00 00]; @@ -611,6 +805,10 @@ fsps,port-usb20-per-port-pe-txi-set = [07 07 06 06 07 07 07 01]; fsps,port-usb20-per-port-txi-set = [00 02 00 00 00 00 00 03];
+ fsps,lpss-s0ix-enable = <1>; + fsps,usb-otg = <0>; + fsps,monitor-mwait-enable = <0>; + /* * TODO(sjg@chromium.org): Move this to the I2C nodes * Intel Common SoC Config diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index ef4dabbe26e..af0397ff1f4 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x3d00 CONFIG_NR_DRAM_BANKS=8 CONFIG_SPL_DM_SPI=y CONFIG_SPL_TEXT_BASE=0xfef10000 +CONFIG_MAX_CPUS=8 CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000 CONFIG_BOOTSTAGE_STASH_ADDR=0xfef00000 CONFIG_DEBUG_UART_BOARD_INIT=y @@ -14,9 +15,10 @@ CONFIG_VENDOR_GOOGLE=y CONFIG_TARGET_CHROMEBOOK_CORAL=y CONFIG_DEBUG_UART=y CONFIG_FSP_VERSION2=y +CONFIG_GENERATE_ACPI_TABLE=y CONFIG_HAVE_ACPI_RESUME=y CONFIG_INTEL_CAR_CQOS=y -CONFIG_X86_OFFSET_U_BOOT=0xffe00000 +CONFIG_X86_OFFSET_U_BOOT=0xffd00000 CONFIG_X86_OFFSET_SPL=0xffe80000 CONFIG_INTEL_GENERIC_WIFI=y CONFIG_BOOTSTAGE=y @@ -26,13 +28,14 @@ CONFIG_BOOTSTAGE_REPORT=y CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=10 CONFIG_BOOTSTAGE_STASH=y CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro earlyprintk console=tty0 console=ttyS0,115200" +CONFIG_BOOTARGS="console=ttyS2,115200n8 cros_legacy loglevel=9 init=/sbin/init oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw noinitrd vt.global_cursor_default=0 add_efi_memmap boot=local noresume noswap i915.modeset=1 nmi_watchdog=panic,lapic disablevmx=off" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_LOG=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y CONFIG_BLOBLIST=y # CONFIG_TPL_BLOBLIST is not set +CONFIG_BLOBLIST_SIZE=0x30000 CONFIG_BLOBLIST_ADDR=0x100000 CONFIG_HANDOFF=y CONFIG_TPL_SYS_MALLOC_SIMPLE=y @@ -74,8 +77,10 @@ CONFIG_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_INTEL_ACPIGEN=y CONFIG_CPU=y +CONFIG_BOARD=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_MISC=y CONFIG_TPL_MISC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y @@ -87,7 +92,9 @@ CONFIG_PINCTRL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_SOUND=y +CONFIG_SOUND_DA7219=y CONFIG_SOUND_I8254=y +CONFIG_SOUND_MAX98357A=y CONFIG_SOUND_RT5677=y CONFIG_SPI=y CONFIG_ICH_SPI=y