From 1e7610bcccf942b7bc2664dee5266b943d03ffc3 Mon Sep 17 00:00:00 2001
From: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Date: Tue, 14 Aug 2007 05:46:37 -0500
Subject: [PATCH] ColdFire MCF52x2: header files update 1

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
---
 include/asm-m68k/immap.h    |  119 +++++++++++++++++++++++
 include/asm-m68k/mcftimer.h |  111 ----------------------
 include/asm-m68k/mcfuart.h  |  217 -------------------------------------------
 3 files changed, 119 insertions(+), 328 deletions(-)
 delete mode 100644 include/asm-m68k/mcftimer.h
 delete mode 100644 include/asm-m68k/mcfuart.h

diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index 2555e7e..677925b 100644
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -26,6 +26,125 @@
 #ifndef __IMMAP_H
 #define __IMMAP_H
 
+#ifdef CONFIG_M5235
+#include <asm/immap_5235.h>
+#include <asm/m5235.h>
+
+#define CFG_FEC0_IOBASE		(MMAP_FEC)
+#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_TMR_BASE		(MMAP_DTMR3)
+#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
+#define CFG_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CFG_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CFG_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
+#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CFG_UDELAY_BASE		(MMAP_PIT0)
+#define CFG_PIT_BASE		(MMAP_PIT1)
+#define CFG_PIT_PRESCALE	(6)
+#endif
+
+#define CFG_INTR_BASE		(MMAP_INTC0)
+#define CFG_NUM_IRQS		(128)
+#endif				/* CONFIG_M5235 */
+
+#ifdef CONFIG_M5249
+#include <asm/immap_5249.h>
+#include <asm/m5249.h>
+
+#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE		(MMAP_INTC)
+#define CFG_NUM_IRQS		(64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_TMR_BASE		(MMAP_DTMR1)
+#define CFG_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
+#define CFG_TMRINTR_NO		(31)
+#define CFG_TMRINTR_MASK	(0x00000400)
+#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI		(0)		/* Level must include inorder to work */
+#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
+#endif
+#endif				/* CONFIG_M5249 */
+
+#ifdef CONFIG_M5271
+#include <asm/immap_5271.h>
+#include <asm/m5271.h>
+
+#define CFG_FEC0_IOBASE		(MMAP_FEC)
+#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_TMR_BASE		(MMAP_DTMR3)
+#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
+#define CFG_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CFG_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI		(0)		/* Level must include inorder to work */
+#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#define CFG_INTR_BASE		(MMAP_INTC0)
+#define CFG_NUM_IRQS		(128)
+#endif				/* CONFIG_M5271 */
+
+#ifdef CONFIG_M5272
+#include <asm/immap_5272.h>
+#include <asm/m5272.h>
+
+#define CFG_FEC0_IOBASE		(MMAP_FEC)
+#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE		(MMAP_INTC)
+#define CFG_NUM_IRQS		(64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE		(MMAP_TMR0)
+#define CFG_TMR_BASE		(MMAP_TMR3)
+#define CFG_TMRPND_REG		(((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr)
+#define CFG_TMRINTR_NO		(INT_TMR3)
+#define CFG_TMRINTR_MASK	(INT_ISR_INT24)
+#define CFG_TMRINTR_PEND	(0)
+#define CFG_TMRINTR_PRI		(INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
+#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif				/* CONFIG_M5272 */
+
+#ifdef CONFIG_M5282
+#include <asm/immap_5282.h>
+#include <asm/m5282.h>
+
+#define CFG_FEC0_IOBASE		(MMAP_FEC)
+#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE		(MMAP_INTC0)
+#define CFG_NUM_IRQS		(128)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_TMR_BASE		(MMAP_DTMR3)
+#define CFG_TMRPND_REG		(((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
+#define CFG_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CFG_TMRINTR_MASK	(1 << INT0_LO_DTMR3)
+#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
+#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif				/* CONFIG_M5282 */
+
 #ifdef CONFIG_M5329
 #include <asm/immap_5329.h>
 #include <asm/m5329.h>
diff --git a/include/asm-m68k/mcftimer.h b/include/asm-m68k/mcftimer.h
deleted file mode 100644
index 381f4eb..0000000
--- a/include/asm-m68k/mcftimer.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * mcftimer.h -- ColdFire internal TIMER support defines.
- *
- * Based on mcftimer.h of uCLinux distribution:
- *      (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
- *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************/
-#ifndef	mcftimer_h
-#define	mcftimer_h
-/****************************************************************************/
-
-#include <linux/config.h>
-
-/*
- *	Get address specific defines for this ColdFire member.
- */
-#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#define	MCFTIMER_BASE1		0x100	/* Base address of TIMER1 */
-#define	MCFTIMER_BASE2		0x120	/* Base address of TIMER2 */
-#elif defined(CONFIG_M5272)
-#define MCFTIMER_BASE1		0x200	/* Base address of TIMER1 */
-#define MCFTIMER_BASE2		0x220	/* Base address of TIMER2 */
-#define MCFTIMER_BASE3		0x240	/* Base address of TIMER4 */
-#define MCFTIMER_BASE4		0x260	/* Base address of TIMER3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#define MCFTIMER_BASE1		0x140	/* Base address of TIMER1 */
-#define MCFTIMER_BASE2		0x180	/* Base address of TIMER2 */
-#elif defined(CONFIG_M5282) | defined(CONFIG_M5271)
-#define MCFTIMER_BASE1		0x150000	/* Base address of TIMER1 */
-#define MCFTIMER_BASE2		0x160000	/* Base address of TIMER2 */
-#define MCFTIMER_BASE3		0x170000	/* Base address of TIMER4 */
-#define MCFTIMER_BASE4		0x180000	/* Base address of TIMER3 */
-#endif
-
-/*
- *	Define the TIMER register set addresses.
- */
-#define	MCFTIMER_TMR		0x00	/* Timer Mode reg (r/w) */
-#define	MCFTIMER_TRR		0x02	/* Timer Reference (r/w) */
-#define	MCFTIMER_TCR		0x04	/* Timer Capture reg (r/w) */
-#define	MCFTIMER_TCN		0x06	/* Timer Counter reg (r/w) */
-#define	MCFTIMER_TER		0x11	/* Timer Event reg (r/w) */
-
-/*
- *	Define the TIMER register set addresses for 5282.
- */
-#define MCFTIMER_PCSR		0
-#define MCFTIMER_PMR		1
-#define MCFTIMER_PCNTR		2
-
-/*
- *	Bit definitions for the Timer Mode Register (TMR).
- *	Register bit flags are common accross ColdFires.
- */
-#define	MCFTIMER_TMR_PREMASK	0xff00	/* Prescalar mask */
-#define	MCFTIMER_TMR_DISCE	0x0000	/* Disable capture */
-#define	MCFTIMER_TMR_ANYCE	0x00c0	/* Capture any edge */
-#define	MCFTIMER_TMR_FALLCE	0x0080	/* Capture fallingedge */
-#define	MCFTIMER_TMR_RISECE	0x0040	/* Capture rising edge */
-#define	MCFTIMER_TMR_ENOM	0x0020	/* Enable output toggle */
-#define	MCFTIMER_TMR_DISOM	0x0000	/* Do single output pulse  */
-#define	MCFTIMER_TMR_ENORI	0x0010	/* Enable ref interrupt */
-#define	MCFTIMER_TMR_DISORI	0x0000	/* Disable ref interrupt */
-#define	MCFTIMER_TMR_RESTART	0x0008	/* Restart counter */
-#define	MCFTIMER_TMR_FREERUN	0x0000	/* Free running counter */
-#define	MCFTIMER_TMR_CLKTIN	0x0006	/* Input clock is TIN */
-#define	MCFTIMER_TMR_CLK16	0x0004	/* Input clock is /16 */
-#define	MCFTIMER_TMR_CLK1	0x0002	/* Input clock is /1 */
-#define	MCFTIMER_TMR_CLKSTOP	0x0000	/* Stop counter */
-#define	MCFTIMER_TMR_ENABLE	0x0001	/* Enable timer */
-#define	MCFTIMER_TMR_DISABLE	0x0000	/* Disable timer */
-
-/*
- *	Bit definitions for the Timer Event Registers (TER).
- */
-#define	MCFTIMER_TER_CAP	0x01	/* Capture event */
-#define	MCFTIMER_TER_REF	0x02	/* Refernece event */
-
-/*
- *	Bit definitions for the 5282 PIT Control and Status Register (PCSR).
- */
-#define MCFTIMER_PCSR_EN	0x0001
-#define MCFTIMER_PCSR_RLD	0x0002
-#define MCFTIMER_PCSR_PIF	0x0004
-#define MCFTIMER_PCSR_PIE	0x0008
-#define MCFTIMER_PCSR_OVW	0x0010
-#define MCFTIMER_PCSR_HALTED	0x0020
-#define MCFTIMER_PCSR_DOZE	0x0040
-
-/****************************************************************************/
-#endif				/* mcftimer_h */
diff --git a/include/asm-m68k/mcfuart.h b/include/asm-m68k/mcfuart.h
deleted file mode 100644
index 1ccc43f..0000000
--- a/include/asm-m68k/mcfuart.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * mcfuart.h -- ColdFire internal UART support defines.
- *
- * File copied from mcfuart.h of uCLinux distribution:
- *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
- *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************/
-#ifndef	mcfuart_h
-#define	mcfuart_h
-/****************************************************************************/
-
-#include <linux/config.h>
-
-/*
- *	Define the base address of the UARTS within the MBAR address
- *	space.
- */
-#if defined(CONFIG_M5272)
-#define	MCFUART_BASE1		0x100	/* Base address of UART1 */
-#define	MCFUART_BASE2		0x140	/* Base address of UART2 */
-#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#if defined(CONFIG_NETtel)
-#define	MCFUART_BASE1		0x180	/* Base address of UART1 */
-#define	MCFUART_BASE2		0x140	/* Base address of UART2 */
-#else
-#define	MCFUART_BASE1		0x140	/* Base address of UART1 */
-#define	MCFUART_BASE2		0x180	/* Base address of UART2 */
-#endif
-#elif defined(CONFIG_M5282) || defined(CONFIG_M5271)
-#define MCFUART_BASE1		0x200	/* Base address of UART1 */
-#define MCFUART_BASE2		0x240	/* Base address of UART2 */
-#define MCFUART_BASE3		0x280	/* Base address of UART3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
-#define MCFUART_BASE1		0x200	/* Base address of UART1 */
-#define MCFUART_BASE2		0x1c0	/* Base address of UART2 */
-#else
-#define MCFUART_BASE1		0x1c0	/* Base address of UART1 */
-#define MCFUART_BASE2		0x200	/* Base address of UART2 */
-#endif
-#endif
-
-/*
- *	Define the ColdFire UART register set addresses.
- */
-#define	MCFUART_UMR		0x00	/* Mode register (r/w) */
-#define	MCFUART_USR		0x04	/* Status register (r) */
-#define	MCFUART_UCSR		0x04	/* Clock Select (w) */
-#define	MCFUART_UCR		0x08	/* Command register (w) */
-#define	MCFUART_URB		0x0c	/* Receiver Buffer (r) */
-#define	MCFUART_UTB		0x0c	/* Transmit Buffer (w) */
-#define	MCFUART_UIPCR		0x10	/* Input Port Change (r) */
-#define	MCFUART_UACR		0x10	/* Auxiliary Control (w) */
-#define	MCFUART_UISR		0x14	/* Interrup Status (r) */
-#define	MCFUART_UIMR		0x14	/* Interrupt Mask (w) */
-#define	MCFUART_UBG1		0x18	/* Baud Rate MSB (r/w) */
-#define	MCFUART_UBG2		0x1c	/* Baud Rate LSB (r/w) */
-#ifdef	CONFIG_M5272
-#define	MCFUART_UTF		0x28	/* Transmitter FIFO (r/w) */
-#define	MCFUART_URF		0x2c	/* Receiver FIFO (r/w) */
-#define	MCFUART_UFPD		0x30	/* Frac Prec. Divider (r/w) */
-#else
-#define	MCFUART_UIVR		0x30	/* Interrupt Vector (r/w) */
-#endif
-#define	MCFUART_UIPR		0x34	/* Input Port (r) */
-#define	MCFUART_UOP1		0x38	/* Output Port Bit Set (w) */
-#define	MCFUART_UOP0		0x3c	/* Output Port Bit Reset (w) */
-
-#ifdef	CONFIG_M5249
-/* Note: This isn't in the 5249 docs */
-#define	MCFUART_UFPD		0x30	/* Frac Prec. Divider (r/w) */
-#endif
-
-/*
- *	Define bit flags in Mode Register 1 (MR1).
- */
-#define	MCFUART_MR1_RXRTS	0x80	/* Auto RTS flow control */
-#define	MCFUART_MR1_RXIRQFULL	0x40	/* RX IRQ type FULL */
-#define	MCFUART_MR1_RXIRQRDY	0x00	/* RX IRQ type RDY */
-#define	MCFUART_MR1_RXERRBLOCK	0x20	/* RX block error mode */
-#define	MCFUART_MR1_RXERRCHAR	0x00	/* RX char error mode */
-
-#define	MCFUART_MR1_PARITYNONE	0x10	/* No parity */
-#define	MCFUART_MR1_PARITYEVEN	0x00	/* Even parity */
-#define	MCFUART_MR1_PARITYODD	0x04	/* Odd parity */
-#define	MCFUART_MR1_PARITYSPACE	0x08	/* Space parity */
-#define	MCFUART_MR1_PARITYMARK	0x0c	/* Mark parity */
-
-#define	MCFUART_MR1_CS5		0x00	/* 5 bits per char */
-#define	MCFUART_MR1_CS6		0x01	/* 6 bits per char */
-#define	MCFUART_MR1_CS7		0x02	/* 7 bits per char */
-#define	MCFUART_MR1_CS8		0x03	/* 8 bits per char */
-
-/*
- *	Define bit flags in Mode Register 2 (MR2).
- */
-#define	MCFUART_MR2_LOOPBACK	0x80	/* Loopback mode */
-#define	MCFUART_MR2_REMOTELOOP	0xc0	/* Remote loopback mode */
-#define	MCFUART_MR2_AUTOECHO	0x40	/* Automatic echo */
-#define	MCFUART_MR2_TXRTS	0x20	/* Assert RTS on TX */
-#define	MCFUART_MR2_TXCTS	0x10	/* Auto CTS flow control */
-
-#define	MCFUART_MR2_STOP1	0x07	/* 1 stop bit */
-#define	MCFUART_MR2_STOP15	0x08	/* 1.5 stop bits */
-#define	MCFUART_MR2_STOP2	0x0f	/* 2 stop bits */
-
-/*
- *	Define bit flags in Status Register (USR).
- */
-#define	MCFUART_USR_RXBREAK	0x80	/* Received BREAK */
-#define	MCFUART_USR_RXFRAMING	0x40	/* Received framing error */
-#define	MCFUART_USR_RXPARITY	0x20	/* Received parity error */
-#define	MCFUART_USR_RXOVERRUN	0x10	/* Received overrun error */
-#define	MCFUART_USR_TXEMPTY	0x08	/* Transmitter empty */
-#define	MCFUART_USR_TXREADY	0x04	/* Transmitter ready */
-#define	MCFUART_USR_RXFULL	0x02	/* Receiver full */
-#define	MCFUART_USR_RXREADY	0x01	/* Receiver ready */
-
-#define	MCFUART_USR_RXERR	(MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
-				MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
-
-/*
- *	Define bit flags in Clock Select Register (UCSR).
- */
-#define	MCFUART_UCSR_RXCLKTIMER	0xd0	/* RX clock is timer */
-#define	MCFUART_UCSR_RXCLKEXT16	0xe0	/* RX clock is external x16 */
-#define	MCFUART_UCSR_RXCLKEXT1	0xf0	/* RX clock is external x1 */
-
-#define	MCFUART_UCSR_TXCLKTIMER	0x0d	/* TX clock is timer */
-#define	MCFUART_UCSR_TXCLKEXT16	0x0e	/* TX clock is external x16 */
-#define	MCFUART_UCSR_TXCLKEXT1	0x0f	/* TX clock is external x1 */
-
-/*
- *	Define bit flags in Command Register (UCR).
- */
-#define	MCFUART_UCR_CMDNULL		0x00	/* No command */
-#define	MCFUART_UCR_CMDRESETMRPTR	0x10	/* Reset MR pointer */
-#define	MCFUART_UCR_CMDRESETRX		0x20	/* Reset receiver */
-#define	MCFUART_UCR_CMDRESETTX		0x30	/* Reset transmitter */
-#define	MCFUART_UCR_CMDRESETERR		0x40	/* Reset error status */
-#define	MCFUART_UCR_CMDRESETBREAK	0x50	/* Reset BREAK change */
-#define	MCFUART_UCR_CMDBREAKSTART	0x60	/* Start BREAK */
-#define	MCFUART_UCR_CMDBREAKSTOP	0x70	/* Stop BREAK */
-
-#define	MCFUART_UCR_TXNULL	0x00	/* No TX command */
-#define	MCFUART_UCR_TXENABLE	0x04	/* Enable TX */
-#define	MCFUART_UCR_TXDISABLE	0x08	/* Disable TX */
-#define	MCFUART_UCR_RXNULL	0x00	/* No RX command */
-#define	MCFUART_UCR_RXENABLE	0x01	/* Enable RX */
-#define	MCFUART_UCR_RXDISABLE	0x02	/* Disable RX */
-
-/*
- *	Define bit flags in Input Port Change Register (UIPCR).
- */
-#define	MCFUART_UIPCR_CTSCOS	0x10	/* CTS change of state */
-#define	MCFUART_UIPCR_CTS	0x01	/* CTS value */
-
-/*
- *	Define bit flags in Input Port Register (UIP).
- */
-#define	MCFUART_UIPR_CTS	0x01	/* CTS value */
-
-/*
- *	Define bit flags in Output Port Registers (UOP).
- *	Clear bit by writing to UOP0, set by writing to UOP1.
- */
-#define	MCFUART_UOP_RTS		0x01	/* RTS set or clear */
-
-/*
- *	Define bit flags in the Auxiliary Control Register (UACR).
- */
-#define	MCFUART_UACR_IEC	0x01	/* Input enable control */
-
-/*
- *	Define bit flags in Interrupt Status Register (UISR).
- *	These same bits are used for the Interrupt Mask Register (UIMR).
- */
-#define	MCFUART_UIR_COS		0x80	/* Change of state (CTS) */
-#define	MCFUART_UIR_DELTABREAK	0x04	/* Break start or stop */
-#define	MCFUART_UIR_RXREADY	0x02	/* Receiver ready */
-#define	MCFUART_UIR_TXREADY	0x01	/* Transmitter ready */
-
-#ifdef	CONFIG_M5272
-/*
- *	Define bit flags in the Transmitter FIFO Register (UTF).
- */
-#define	MCFUART_UTF_TXB		0x1f	/* transmitter data level */
-#define	MCFUART_UTF_FULL	0x20	/* transmitter fifo full */
-#define	MCFUART_UTF_TXS		0xc0	/* transmitter status */
-
-/*
- *	Define bit flags in the Receiver FIFO Register (URF).
- */
-#define	MCFUART_URF_RXB		0x1f	/* receiver data level */
-#define	MCFUART_URF_FULL	0x20	/* receiver fifo full */
-#define	MCFUART_URF_RXS		0xc0	/* receiver status */
-#endif
-- 
1.5.2

