8 May
2020
8 May
'20
1:57 p.m.
On 5/8/20 1:49 PM, Fabio Estevam wrote:
On Fri, May 8, 2020 at 1:53 AM Fabio Estevam festevam@gmail.com wrote:
Hi Marek,
On Thu, May 7, 2020 at 11:56 PM Fabio Estevam festevam@gmail.com wrote:
I will activate them on SPL tomorrow.
After activating the SPL clocks I see:
clk 69 [ ] imx_clk_gate2 | | `-- dram1_root_clk
The dram1_root_clk is not getting turned on.
Looks at the iMX8MM EVK log: https://pastebin.com/raw/XVc6AAvr
It also has:
[ ] clk_gate | | `-- dram_pll_out
So it seems the problem is somewhere else.
Maybe you also need entries like 126dcc925d ("ARM: imx: imx8mm: Add missing clock entries for FEC clock") for MX8MP ?