Hello,
I am working on porting U-Boot 2014.07 to a custom TI AM3354 based hardware platform and am confused trying to set the pin mux for the two Ethernet interfaces that are on the board.
RGMII1_ pins are connected to an ATHEROS AR8031 PHY (PHY ADDR 04) and the pins GPMC_A0 .. GPMC_A11 are connected to a Micrel KSZ8041NL (PHY ADDR 01). The output of the "mii info" command looks OK so the MDIO interface looks to be OK as it gives:
PHY 0x00: OUI = 0x0885, Model = 0x11, Rev = 0x03, 10baseT, HDX PHY 0x01: OUI = 0x0885, Model = 0x11, Rev = 0x03, 10baseT, HDX PHY 0x04: OUI = 0x1374, Model = 0x07, Rev = 0x04, 1000baseX, FDX
However, with debug enabled, it is reporting the PHYs incorrectly as it gives:
cpsw connected to Micrel KSZ804 cpsw connected to Micrel KSZ804 cpsw
The AR8031 provides a connection to the outside world and the KSZ8041 connects to an Ethernet switch which then connects on to other devices on the board to form a private network. The DHCP command just sits in a loop waiting for PHY auto negotiation to complete but timing out!
In the SPL code I am setting up the pin mux as follows:
static struct module_pin_mux rgmii1_pin_mux[] = { {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ {-1}, };
static struct module_pin_mux rmii2_pin_mux[] = { {OFFSET(gpmc_a0), MODE(2)}, /* RMII2_TXEN */ {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RMII2_RXDV */ {OFFSET(gpmc_a2), MODE(2)}, /* RMII2_TXD3 */ {OFFSET(gpmc_a3), MODE(2)}, /* RMII2_TXD2 */ {OFFSET(gpmc_a4), MODE(2)}, /* RMII2_TXD1 */ {OFFSET(gpmc_a5), MODE(2)}, /* RMII2_TXD0 */ {OFFSET(gpmc_a6), MODE(2)}, /* RMII2_TXCLK */ {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RMII2_RXCLK */ {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RMII2_RXD3 */ {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RMII2_RXD2 */ {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RMII2_RXD1 */ {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RMII2_RXD0 */ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ {-1}, };
Any help would be much appreciated?
Thanks,
Andy.