This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is the last ARCH_MPC837X platform, remove that support as well.
Cc: Priyanka Jain priyanka.jain@nxp.com Signed-off-by: Tom Rini trini@konsulko.com --- arch/powerpc/cpu/mpc83xx/Kconfig | 21 - arch/powerpc/cpu/mpc83xx/hrcw/Kconfig | 52 ++- arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr | 2 +- arch/powerpc/cpu/mpc83xx/speed.c | 34 +- arch/powerpc/include/asm/arch-mpc83xx/gpio.h | 3 +- arch/powerpc/include/asm/global_data.h | 7 +- arch/powerpc/include/asm/immap_83xx.h | 44 --- arch/powerpc/include/asm/mpc8xxx_spi.h | 3 +- board/freescale/mpc837xemds/Kconfig | 12 - board/freescale/mpc837xemds/MAINTAINERS | 8 - board/freescale/mpc837xemds/Makefile | 7 - board/freescale/mpc837xemds/README | 104 ----- board/freescale/mpc837xemds/mpc837xemds.c | 354 ----------------- board/freescale/mpc837xemds/pci.c | 149 ------- board/freescale/mpc837xemds/pci.h | 6 - configs/MPC837XEMDS_HOST_defconfig | 190 --------- configs/MPC837XEMDS_SLAVE_defconfig | 143 ------- configs/MPC837XEMDS_defconfig | 166 -------- drivers/ram/mpc83xx_sdram.c | 12 +- include/configs/MPC837XEMDS.h | 370 ------------------ include/mpc83xx.h | 114 +----- 21 files changed, 51 insertions(+), 1750 deletions(-) delete mode 100644 board/freescale/mpc837xemds/Kconfig delete mode 100644 board/freescale/mpc837xemds/MAINTAINERS delete mode 100644 board/freescale/mpc837xemds/Makefile delete mode 100644 board/freescale/mpc837xemds/README delete mode 100644 board/freescale/mpc837xemds/mpc837xemds.c delete mode 100644 board/freescale/mpc837xemds/pci.c delete mode 100644 board/freescale/mpc837xemds/pci.h delete mode 100644 configs/MPC837XEMDS_HOST_defconfig delete mode 100644 configs/MPC837XEMDS_SLAVE_defconfig delete mode 100644 configs/MPC837XEMDS_defconfig delete mode 100644 include/configs/MPC837XEMDS.h
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index b13a555413ec..4b5ad5bb0173 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -75,13 +75,6 @@ config TARGET_MPC8349ITX select ARCH_MPC8349 imply CMD_IRQ
-config TARGET_MPC837XEMDS - bool "Support MPC837XEMDS" - select ARCH_MPC837X - select BOARD_EARLY_INIT_F - imply CMD_SATA - imply FSL_SATA - config TARGET_IDS8313 bool "Support ids8313" select ARCH_MPC8313 @@ -251,19 +244,6 @@ config ARCH_MPC8360 select MPC83XX_LDP_PIN select MPC83XX_SECOND_I2C_SUPPORT
-config ARCH_MPC837X - bool - select MPC83XX_PCI_SUPPORT - select MPC83XX_TSEC1_SUPPORT - select MPC83XX_TSEC2_SUPPORT - select MPC83XX_PCIE1_SUPPORT - select MPC83XX_PCIE2_SUPPORT - select MPC83XX_SDHC_SUPPORT - select MPC83XX_SATA_SUPPORT - select MPC83XX_LDP_PIN - select MPC83XX_SECOND_I2C_SUPPORT - select FSL_ELBC - config SYS_IMMR hex "Value for IMMR" default 0xE0000000 @@ -316,7 +296,6 @@ source "board/freescale/mpc8323erdb/Kconfig" source "board/freescale/mpc832xemds/Kconfig" source "board/freescale/mpc8349emds/Kconfig" source "board/freescale/mpc8349itx/Kconfig" -source "board/freescale/mpc837xemds/Kconfig" source "board/ids/ids8313/Kconfig" source "board/keymile/Kconfig" source "board/mpc8308_p1m/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig index c657a47b1143..b88c8938b94f 100644 --- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig @@ -7,7 +7,7 @@ config LBMC_CLOCK_MODE_1_1 bool "1 : 1"
config LBMC_CLOCK_MODE_1_2 - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + depends on ARCH_MPC8349 || ARCH_MPC8360 bool "1 : 2"
endchoice @@ -19,7 +19,7 @@ config DDR_MC_CLOCK_MODE_1_2 bool "1 : 2"
config DDR_MC_CLOCK_MODE_1_1 - depends on ARCH_MPC8315 || ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + depends on ARCH_MPC8315 || ARCH_MPC8349 || ARCH_MPC8360 bool "1 : 1"
endchoice @@ -30,7 +30,6 @@ choice prompt "System PLL VCO division"
config SYSTEM_PLL_VCO_DIV_1 - depends on !ARCH_MPC837X bool "1"
config SYSTEM_PLL_VCO_DIV_2 @@ -67,39 +66,39 @@ config SYSTEM_PLL_FACTOR_6_1 bool "6 : 1"
config SYSTEM_PLL_FACTOR_7_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPC8349 || ARCH_MPV8360 bool "7 : 1"
config SYSTEM_PLL_FACTOR_8_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPC8349 || ARCH_MPV8360 bool "8 : 1"
config SYSTEM_PLL_FACTOR_9_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPC8349 || ARCH_MPV8360 bool "9 : 1"
config SYSTEM_PLL_FACTOR_10_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPC8349 || ARCH_MPV8360 bool "10 : 1"
config SYSTEM_PLL_FACTOR_11_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPC8349 || ARCH_MPV8360 bool "11 : 1"
config SYSTEM_PLL_FACTOR_12_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPC8349 || ARCH_MPV8360 bool "12 : 1"
config SYSTEM_PLL_FACTOR_13_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPC8349 || ARCH_MPV8360 bool "13 : 1"
config SYSTEM_PLL_FACTOR_14_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPC8349 || ARCH_MPV8360 bool "14 : 1"
config SYSTEM_PLL_FACTOR_15_1 - depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + depends on ARCH_MPC8349 || ARCH_MPV8360 bool "15 : 1"
config SYSTEM_PLL_FACTOR_16_1 @@ -430,10 +429,6 @@ config BOOT_ROM_INTERFACE_PCI2 depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349 bool "PCI2"
-config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM - depends on ARCH_MPC837X - bool "PCI2" - config BOOT_ROM_INTERFACE_ESDHC depends on ARCH_MPC8309 bool "eSDHC" @@ -449,7 +444,7 @@ config BOOT_ROM_INTERFACE_GPCM_16BIT bool "Local bus GPCM - 16-bit ROM"
config BOOT_ROM_INTERFACE_GPCM_32BIT - depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + depends on ARCH_MPC8349 || ARCH_MPC8360 bool "Local bus GPCM - 32-bit ROM"
config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL @@ -479,7 +474,7 @@ config TSEC1_MODE_RGMII bool "RGMII"
config TSEC1_MODE_RTBI - depends on ARCH_MPC831X || ARCH_MPC837X + depends on ARCH_MPC831X bool "RTBI"
config TSEC1_MODE_GMII @@ -491,7 +486,7 @@ config TSEC1_MODE_TBI bool "TBI"
config TSEC1_MODE_SGMII - depends on ARCH_MPC831X || ARCH_MPC837X + depends on ARCH_MPC831X bool "SGMII"
endchoice @@ -515,7 +510,7 @@ config TSEC2_MODE_RGMII bool "RGMII"
config TSEC2_MODE_RTBI - depends on ARCH_MPC831X || ARCH_MPC837X + depends on ARCH_MPC831X bool "RTBI"
config TSEC2_MODE_GMII @@ -527,7 +522,7 @@ config TSEC2_MODE_TBI bool "TBI"
config TSEC2_MODE_SGMII - depends on ARCH_MPC831X || ARCH_MPC837X + depends on ARCH_MPC831X bool "SGMII"
endchoice @@ -606,12 +601,12 @@ config SYSTEM_PLL_VCO_DIV int default 0 if ARCH_MPC8349 || ARCH_MPC832X default 2 if ARCH_MPC8313 - default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X - default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X - default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X - default 0 if SYSTEM_PLL_VCO_DIV_4 && (ARCH_MPC8360 || ARCH_MPC837X) - default 1 if SYSTEM_PLL_VCO_DIV_8 && (ARCH_MPC8360 || ARCH_MPC837X) - default 2 if SYSTEM_PLL_VCO_DIV_2 && (ARCH_MPC8360 || ARCH_MPC837X) + default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 + default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 + default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 + default 0 if SYSTEM_PLL_VCO_DIV_4 && (ARCH_MPC8360) + default 1 if SYSTEM_PLL_VCO_DIV_8 && (ARCH_MPC8360) + default 2 if SYSTEM_PLL_VCO_DIV_2 && (ARCH_MPC8360) default 3 if SYSTEM_PLL_VCO_DIV_1
config SYSTEM_PLL_FACTOR @@ -679,7 +674,6 @@ config BOOT_ROM_INTERFACE default 0x8 if BOOT_ROM_INTERFACE_PCI2 default 0x8 if BOOT_ROM_INTERFACE_ESDHC default 0xc if BOOT_ROM_INTERFACE_SPI - default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT default 0x1c if BOOT_ROM_INTERFACE_GPCM_32BIT @@ -725,7 +719,7 @@ config TRUE_LITTLE_ENDIAN
config LALE_TIMING int - default 0 if ARCH_MPC830X || ARCH_MPC837X + default 0 if ARCH_MPC830X default 0 if LALE_TIMING_NORMAL default 1 if LALE_TIMING_EARLIER
diff --git a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr index f32309e6c0f0..b7a38a5a7837 100644 --- a/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr +++ b/arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr @@ -14,7 +14,7 @@ config SPCR_OPT_SPEC_READ
endchoice
-if ARCH_MPC8308 || ARCH_MPC831X || ARCH_MPC837X +if ARCH_MPC8308 || ARCH_MPC831X
choice prompt "TSEC emergency priority" diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 58e197f12082..dcfd5bb82bb7 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -89,7 +89,7 @@ int get_clocks(void)
u32 csb_clk; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) + defined(CONFIG_ARCH_MPC834X) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; @@ -125,12 +125,11 @@ int get_clocks(void) u32 qe_clk; u32 brg_clk; #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC837X) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) u32 pciexp1_clk; u32 pciexp2_clk; #endif -#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) u32 sata_clk; #endif
@@ -159,7 +158,7 @@ int get_clocks(void) sccr = im->clk.sccr;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) + defined(CONFIG_ARCH_MPC834X) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -180,7 +179,7 @@ int get_clocks(void) #endif
#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) + defined(CONFIG_ARCH_MPC834X) switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { case 0: usbdr_clk = 0; @@ -201,7 +200,7 @@ int get_clocks(void) #endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) + defined(CONFIG_ARCH_MPC834X) switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { case 0: tsec2_clk = 0; @@ -324,8 +323,6 @@ int get_clocks(void) i2c1_clk = enc_clk; #elif defined(CONFIG_FSL_ESDHC) i2c1_clk = sdhc_clk; -#elif defined(CONFIG_ARCH_MPC837X) - i2c1_clk = enc_clk; #elif defined(CONFIG_ARCH_MPC8309) i2c1_clk = csb_clk; #endif @@ -333,8 +330,7 @@ int get_clocks(void) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ #endif
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC837X) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { case 0: pciexp1_clk = 0; @@ -372,7 +368,7 @@ int get_clocks(void) } #endif
-#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { case 0: sata_clk = 0; @@ -452,7 +448,7 @@ int get_clocks(void)
gd->arch.csb_clk = csb_clk; #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) + defined(CONFIG_ARCH_MPC834X) gd->arch.tsec1_clk = tsec1_clk; gd->arch.tsec2_clk = tsec2_clk; gd->arch.usbdr_clk = usbdr_clk; @@ -486,12 +482,11 @@ int get_clocks(void) gd->arch.qe_clk = qe_clk; gd->arch.brg_clk = brg_clk; #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC837X) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) gd->arch.pciexp1_clk = pciexp1_clk; gd->arch.pciexp2_clk = pciexp2_clk; #endif -#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) gd->arch.sata_clk = sata_clk; #endif gd->pci_clk = pci_sync_in; @@ -568,7 +563,7 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc, strmhz(buf, gd->arch.sdhc_clk)); #endif #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) + defined(CONFIG_ARCH_MPC834X) printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->arch.tsec1_clk)); printf(" TSEC2: %-4s MHz\n", @@ -583,14 +578,13 @@ static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc, printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->arch.usbmph_clk)); #endif -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC837X) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->arch.pciexp1_clk)); printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->arch.pciexp2_clk)); #endif -#if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) +#if defined(CONFIG_ARCH_MPC8315) printf(" SATA: %-4s MHz\n", strmhz(buf, gd->arch.sata_clk)); #endif diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h index 8a6896e6229c..48fd062331bb 100644 --- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -9,8 +9,7 @@ #if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_ARCH_MPC8315) #define MPC83XX_GPIO_CTRLRS 1 -#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) || \ - defined(CONFIG_ARCH_MPC8309) +#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8309) #define MPC83XX_GPIO_CTRLRS 2 #else #define MPC83XX_GPIO_CTRLRS 0 diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 192a02d347e7..42a8a17c2dcf 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -35,7 +35,7 @@ struct arch_global_data { /* There are other clocks in the MPC83XX */ u32 csb_clk; # if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X) + defined(CONFIG_ARCH_MPC834X) u32 tsec1_clk; u32 tsec2_clk; u32 usbdr_clk; @@ -52,12 +52,11 @@ struct arch_global_data { u32 enc_clk; u32 lbiu_clk; u32 lclk_clk; -# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC837X) +# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) u32 pciexp1_clk; u32 pciexp2_clk; # endif -# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315) +# if defined(CONFIG_ARCH_MPC8315) u32 sata_clk; # endif # if defined(CONFIG_ARCH_MPC8360) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index a03f938d9f49..073ae40a6568 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -795,50 +795,6 @@ typedef struct immap { u8 res9[0x1CF00]; } immap_t;
-#elif defined(CONFIG_ARCH_MPC837X) -typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - gpio83xx_t gpio[2]; /* General purpose I/O module */ - u8 res0[0x1200]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res1[0x1300]; - duart83xx_t duart[2]; /* DUART */ - u8 res2[0x900]; - fsl_lbc_t im_lbc; /* Local Bus Controller Regs */ - u8 res3[0x1000]; - spi8xxx_t spi; /* Serial Peripheral Interface */ - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res4[0x80]; - ios83xx_t ios; /* Sequencer */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res5[0xa00]; - pex83xx_t pciexp[2]; /* PCI Express Controller */ - u8 res6[0xd000]; - sata83xx_t sata[4]; /* SATA Controller */ - u8 res7[0x7000]; - usb83xx_t usb[1]; /* USB DR Controller */ - tsec83xx_t tsec[2]; - u8 res8[0x8000]; - sdhc83xx_t sdhc; /* SDHC Controller */ - u8 res9[0x1000]; - security83xx_t security; - u8 res10[0xA3000]; - serdes83xx_t serdes[2]; /* SerDes Registers */ - u8 res11[0xCE00]; - rom83xx_t rom; /* On Chip ROM */ -} immap_t; - #elif defined(CONFIG_ARCH_MPC8360) typedef struct immap { sysconf83xx_t sysconf; /* System configuration */ diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 470ee955f303..470add7cbf3e 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -14,8 +14,7 @@ defined(CONFIG_ARCH_MPC8309) || \ defined(CONFIG_ARCH_MPC8313) || \ defined(CONFIG_ARCH_MPC8315) || \ - defined(CONFIG_ARCH_MPC834X) || \ - defined(CONFIG_ARCH_MPC837X) + defined(CONFIG_ARCH_MPC834X)
typedef struct spi8xxx { u8 res0[0x20]; /* 0x0-0x01f reserved */ diff --git a/board/freescale/mpc837xemds/Kconfig b/board/freescale/mpc837xemds/Kconfig deleted file mode 100644 index 20d29db09916..000000000000 --- a/board/freescale/mpc837xemds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC837XEMDS - -config SYS_BOARD - default "mpc837xemds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC837XEMDS" - -endif diff --git a/board/freescale/mpc837xemds/MAINTAINERS b/board/freescale/mpc837xemds/MAINTAINERS deleted file mode 100644 index ce9c446f2df3..000000000000 --- a/board/freescale/mpc837xemds/MAINTAINERS +++ /dev/null @@ -1,8 +0,0 @@ -MPC837XEMDS BOARD -#M: Dave Liu daveliu@freescale.com -S: Orphan (since 2018-05) -F: board/freescale/mpc837xemds/ -F: include/configs/MPC837XEMDS.h -F: configs/MPC837XEMDS_defconfig -F: configs/MPC837XEMDS_SLAVE_defconfig -F: configs/MPC837XEMDS_HOST_defconfig diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile deleted file mode 100644 index 5348cdf00cc5..000000000000 --- a/board/freescale/mpc837xemds/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc837xemds.o -obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/mpc837xemds/README b/board/freescale/mpc837xemds/README deleted file mode 100644 index dbb15171e60f..000000000000 --- a/board/freescale/mpc837xemds/README +++ /dev/null @@ -1,104 +0,0 @@ -Freescale MPC837xEMDS Board ------------------------------------------ -1. Board Switches and Jumpers -1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board - For some reason, the HW designers describe the switch settings - in terms of 0 and 1, and then map that to physical switches where - the label "On" refers to logic 0 and "Off" is logic 1. - - Switch bits are numbered 1 through, like, 4 6 8 or 10, but the - bits may contribute to signals that are numbered based at 0, - and some of those signals may be high-bit-number-0 too. Heed - well the names and labels and do not get confused. - - "Off" == 1 - "On" == 0 - - SW4[8] is the bit labeled 8 on Switch 4. - SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. - SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On" - and bits labeled 8 is set as "Off". - -1.1 For the MPC837xEMDS Processor Board - - First, make sure the board default setting is consistent with the - document shipped with your board. Then apply the following setting: - SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting) - SW4[1-8]= 0000_0110 (core PLL setting) - SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash) - SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH) - SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII) - J3 2-3, TSEC1 LVDD1 with 2.5V - J6 2-3, TSEC2 LVDD2 with 2.5V - J9 2-3, CLKIN from osc on board - J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND - J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND) - mounted, HRCW load from BCSR. - - on board Oscillator: 66M - -2. Memory Map - -2.1. The memory map should look pretty much like this: - - 0x0000_0000 0x7fff_ffff DDR 2G - 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M - 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M - 0xc000_0000 0xdfff_ffff Empty 512M - 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M - 0xe010_0000 0xe02f_ffff Empty 2M - 0xe030_0000 0xe03f_ffff PCI IO 1M - 0xe040_0000 0xe05f_ffff Empty 2M - 0xe060_0000 0xe060_7fff NAND Flash 32K - 0xf400_0000 0xf7ff_ffff Empty 64M - 0xf800_0000 0xf800_7fff BCSR on CS1 32K - 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M - -3. Definitions - -3.1 Explanation of NEW definitions in: - - include/configs/MPC837XEMDS.h - - CONFIG_MPC83xx MPC83xx family for both MPC837x and MPC8360 - CONFIG_MPC837x MPC837x specific - CONFIG_MPC837XEMDS MPC837XEMDS board specific - -4. Compilation - - Assuming you're using BASH shell: - - export CROSS_COMPILE=your-cross-compile-prefix - cd u-boot - make distclean - make MPC837XEMDS_config - make - -5. Downloading and Flashing Images - -5.0 Download over serial line using Kermit: - - loadb - [Drop to kermit: - ^\c - send <u-boot-bin-image> - c - ] - - - Or via tftp: - - tftp 40000 u-boot.bin - -5.1 Reflash U-Boot Image using U-Boot - - tftp 40000 u-boot.bin - protect off fe000000 fe1fffff - erase fe000000 fe1fffff - - cp.b 40000 fe000000 xxxx - -You have to supply the correct byte count with 'xxxx' from the TFTP result log. - -6. Notes - 1) The console baudrate for MPC837XEMDS is 115200bps. diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c deleted file mode 100644 index 71875cf8f8ec..000000000000 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2007,2010 Freescale Semiconductor, Inc. - * Dave Liu daveliu@freescale.com - */ - -#include <common.h> -#include <hwconfig.h> -#include <i2c.h> -#include <init.h> -#include <net.h> -#include <asm/bitops.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/fsl_mpc83xx_serdes.h> -#include <spd_sdram.h> -#include <tsec.h> -#include <linux/delay.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <fsl_esdhc.h> -#include <fsl_mdio.h> -#include <phy.h> -#include "pci.h" -#include "../common/pq-mds-pib.h" - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; - - /* Enable flash write */ - bcsr[0x9] &= ~0x04; - /* Clear all of the interrupt of BCSR */ - bcsr[0xe] = 0xff; - -#ifdef CONFIG_FSL_SERDES - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - u32 spridr = in_be32(&immr->sysconf.spridr); - - /* we check only part num, and don't look for CPU revisions */ - switch (PARTID_NO_E(spridr)) { - case SPR_8377: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - break; - case SPR_8378: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII, - FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V); - break; - case SPR_8379: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - break; - default: - printf("serdes not configured: unknown CPU part number: " - "%04x\n", spridr >> 16); - break; - } -#endif /* CONFIG_FSL_SERDES */ - return 0; -} - -#ifdef CONFIG_FSL_ESDHC -int board_mmc_init(struct bd_info *bd) -{ - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; - u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; - - if (!hwconfig("esdhc")) - return 0; - - /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */ - bcsr[0xc] |= 0x4c; - - /* Set proper bits in SICR to allow SD signals through */ - clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); - clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI, - SICRH_GPIO2_E_SD | SICRH_SPI_SD); - - return fsl_esdhc_mmc_init(bd); -} -#endif - -#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) -int board_eth_init(struct bd_info *bd) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[2]; - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; - u32 rcwh = in_be32(&im->reset.rcwh); - u32 tsec_mode; - int num = 0; - - /* New line after Net: */ - printf("\n"); - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - - printf(CONFIG_TSEC1_NAME ": "); - - tsec_mode = rcwh & HRCWH_TSEC1M_MASK; - if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) { - printf("RGMII\n"); - /* this is default, no need to fixup */ - } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) { - printf("SGMII\n"); - tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII; - tsec_info[num].flags = TSEC_GIGABIT; - } else { - printf("unsupported PHY type\n"); - } - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - - printf(CONFIG_TSEC2_NAME ": "); - - tsec_mode = rcwh & HRCWH_TSEC2M_MASK; - if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) { - printf("RGMII\n"); - /* this is default, no need to fixup */ - } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) { - printf("SGMII\n"); - tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII; - tsec_info[num].flags = TSEC_GIGABIT; - } else { - printf("unsupported PHY type\n"); - } - num++; -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bd, &mdio_info); - - return tsec_eth_init(bd, tsec_info, num); -} - -static void __ft_tsec_fixup(void *blob, struct bd_info *bd, const char *alias, - int phy_addr) -{ - const u32 *ph; - int off; - int err; - - off = fdt_path_offset(blob, alias); - if (off < 0) { - printf("WARNING: could not find %s alias: %s.\n", alias, - fdt_strerror(off)); - return; - } - - err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII); - - if (err) { - printf("WARNING: could not set phy-connection-type for %s: " - "%s.\n", alias, fdt_strerror(err)); - return; - } - - ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0); - if (!ph) { - printf("WARNING: could not get phy-handle for %s.\n", - alias); - return; - } - - off = fdt_node_offset_by_phandle(blob, *ph); - if (off < 0) { - printf("WARNING: could not get phy node for %s: %s\n", alias, - fdt_strerror(off)); - return; - } - - phy_addr = cpu_to_fdt32(phy_addr); - err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr)); - if (err < 0) { - printf("WARNING: could not set phy node's reg for %s: " - "%s.\n", alias, fdt_strerror(err)); - return; - } -} - -static void ft_tsec_fixup(void *blob, struct bd_info *bd) -{ - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; - u32 rcwh = in_be32(&im->reset.rcwh); - u32 tsec_mode; - -#ifdef CONFIG_TSEC1 - tsec_mode = rcwh & HRCWH_TSEC1M_MASK; - if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) - __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII); -#endif - -#ifdef CONFIG_TSEC2 - tsec_mode = rcwh & HRCWH_TSEC2M_MASK; - if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) - __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII); -#endif -} -#else -static inline void ft_tsec_fixup(void *blob, struct bd_info *bd) {} -#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */ - -int board_early_init_r(void) -{ -#ifdef CONFIG_PQ_MDS_PIB - pib_init(); -#endif - return 0; -} - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif -int fixed_sdram(void); - -int dram_init(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -ENXIO; - -#if defined(CONFIG_SPD_EEPROM) - msize = spd_sdram(); -#else - msize = fixed_sdram(); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* Initialize DDR ECC byte */ - ddr_enable_ecc(msize * 1024 * 1024); -#endif - - /* return total bus DDR size(bytes) */ - gd->ram_size = msize * 1024 * 1024; - - return 0; -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; - u32 msize_log2 = __ilog2(msize); - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - -#if (CONFIG_SYS_DDR_SIZE != 512) -#warning Currenly any ddr size other than 512 is not supported -#endif - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; - udelay(50000); - - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; - udelay(1000); - - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; - udelay(1000); - - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - __asm__ __volatile__("sync"); - udelay(1000); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - udelay(2000); - return CONFIG_SYS_DDR_SIZE; -} -#endif /*!CONFIG_SYS_SPD_EEPROM */ - -int checkboard(void) -{ - puts("Board: Freescale MPC837xEMDS\n"); - return 0; -} - -#ifdef CONFIG_PCI -int board_pci_host_broken(void) -{ - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; - const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST; - - /* It's always OK in case of external arbiter. */ - if (hwconfig_subarg_cmp("pci", "arbiter", "external")) - return 0; - - if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask) - return 1; - - return 0; -} - -static void ft_pci_fixup(void *blob, struct bd_info *bd) -{ - const char *status = "broken (no arbiter)"; - int off; - int err; - - off = fdt_path_offset(blob, "pci0"); - if (off < 0) { - printf("WARNING: could not find pci0 alias: %s.\n", - fdt_strerror(off)); - return; - } - - err = fdt_setprop(blob, off, "status", status, strlen(status) + 1); - if (err) { - printf("WARNING: could not set status for pci0: %s.\n", - fdt_strerror(err)); - return; - } -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); - ft_tsec_fixup(blob, bd); - fsl_fdt_fixup_dr_usb(blob, bd); - fdt_fixup_esdhc(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); - if (board_pci_host_broken()) - ft_pci_fixup(blob, bd); - ft_pcie_fixup(blob, bd); -#endif - - return 0; -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c deleted file mode 100644 index 188e60ac08c4..000000000000 --- a/board/freescale/mpc837xemds/pci.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - */ - -#include <init.h> -#include <asm/mmu.h> -#include <asm/io.h> -#include <common.h> -#include <env.h> -#include <mpc83xx.h> -#include <pci.h> -#include <i2c.h> -#include <fdt_support.h> -#include <asm/fsl_i2c.h> -#include <asm/fsl_mpc83xx_serdes.h> -#include <linux/delay.h> - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI_MEM_BASE, - phys_start: CONFIG_SYS_PCI_MEM_PHYS, - size: CONFIG_SYS_PCI_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI_MMIO_BASE, - phys_start: CONFIG_SYS_PCI_MMIO_PHYS, - size: CONFIG_SYS_PCI_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI_IO_BASE, - phys_start: CONFIG_SYS_PCI_IO_PHYS, - size: CONFIG_SYS_PCI_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -static struct pci_region pcie_regions_1[] = { - { - .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, - .size = CONFIG_SYS_PCIE2_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE2_IO_BASE, - .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, - .size = CONFIG_SYS_PCIE2_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -static int is_pex_x2(void) -{ - const char *pex_x2 = env_get("pex_x2"); - - if (pex_x2 && !strcmp(pex_x2, "yes")) - return 1; - return 0; -} - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile sysconf83xx_t *sysconf = &immr->sysconf; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *reg[] = { pci_regions }; - struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; - u32 spridr = in_be32(&immr->sysconf.spridr); - int pex2 = is_pex_x2(); - - if (board_pci_host_broken()) - goto skip_pci; - - /* Enable all 5 PCI_CLK_OUTPUTS */ - clk->occr |= 0xf8000000; - udelay(2000); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - udelay(2000); - - mpc83xx_pci_init(1, reg); -skip_pci: - /* There is no PEX in MPC8379 parts. */ - if (PARTID_NO_E(spridr) == SPR_8379) - return; - - if (pex2) - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - else - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - - /* Configure the clock for PCIE controller */ - clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, - SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - if (!pex2) - out_be32(&sysconf->pecr2, 0xE0008000); - udelay(2000); - - /* Configure PCI Express Local Access Windows */ - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); - out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg); -} - -void ft_pcie_fixup(void *blob, struct bd_info *bd) -{ - const char *status = "disabled (PCIE1 is x2)"; - - if (!is_pex_x2()) - return; - - do_fixup_by_path(blob, "pci2", "status", status, - strlen(status) + 1, 1); -} diff --git a/board/freescale/mpc837xemds/pci.h b/board/freescale/mpc837xemds/pci.h deleted file mode 100644 index a56803198889..000000000000 --- a/board/freescale/mpc837xemds/pci.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __BOARD_MPC837XEMDS_PCI_H -#define __BOARD_MPC837XEMDS_PCI_H - -extern void ft_pcie_fixup(void *blob, struct bd_info *bd); - -#endif /* __BOARD_MPC837XEMDS_PCI_H */ diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig deleted file mode 100644 index 7e2e0e4b3b63..000000000000 --- a/configs/MPC837XEMDS_HOST_defconfig +++ /dev/null @@ -1,190 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC837XEMDS=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_6_1=y -CONFIG_CORE_PLL_RATIO_15_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_RGMII=y -CONFIG_TSEC2_MODE_RGMII=y -CONFIG_LDP_PIN_MUX_STATE_0=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM_LOWER" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="SDRAM_UPPER" -CONFIG_BAT1_BASE=0x10000000 -CONFIG_BAT1_LENGTH_256_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="IMMR" -CONFIG_BAT2_BASE=0xE0000000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_INHIBITED=y -CONFIG_BAT2_ICACHE_GUARDED=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="BCSR" -CONFIG_BAT3_BASE=0xF8000000 -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_ICACHE_INHIBITED=y -CONFIG_BAT3_ICACHE_GUARDED=y -CONFIG_BAT3_DCACHE_INHIBITED=y -CONFIG_BAT3_DCACHE_GUARDED=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_BAT4=y -CONFIG_BAT4_NAME="FLASH" -CONFIG_BAT4_BASE=0xFE000000 -CONFIG_BAT4_LENGTH_32_MBYTES=y -CONFIG_BAT4_ACCESS_RW=y -CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT4_DCACHE_INHIBITED=y -CONFIG_BAT4_DCACHE_GUARDED=y -CONFIG_BAT4_USER_MODE_VALID=y -CONFIG_BAT4_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="STACK_IN_DCACHE" -CONFIG_BAT5_BASE=0xE6000000 -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_BAT6=y -CONFIG_BAT6_NAME="PCI_MEM" -CONFIG_BAT6_BASE=0x80000000 -CONFIG_BAT6_LENGTH_256_MBYTES=y -CONFIG_BAT6_ACCESS_RW=y -CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT6_USER_MODE_VALID=y -CONFIG_BAT6_SUPERVISOR_MODE_VALID=y -CONFIG_BAT7=y -CONFIG_BAT7_NAME="PCI_MMIO" -CONFIG_BAT7_BASE=0x90000000 -CONFIG_BAT7_LENGTH_256_MBYTES=y -CONFIG_BAT7_ACCESS_RW=y -CONFIG_BAT7_ICACHE_INHIBITED=y -CONFIG_BAT7_ICACHE_GUARDED=y -CONFIG_BAT7_DCACHE_INHIBITED=y -CONFIG_BAT7_DCACHE_GUARDED=y -CONFIG_BAT7_USER_MODE_VALID=y -CONFIG_BAT7_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xF8000000 -CONFIG_LBLAW1_NAME="BCSR" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_LBLAW3=y -CONFIG_LBLAW3_BASE=0xE0600000 -CONFIG_LBLAW3_NAME="NAND" -CONFIG_LBLAW3_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="BCSR" -CONFIG_BR1_OR1_BASE=0xF8000000 -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_OR1_XACS_EXTENDED=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_OR1_EAD_EXTRA=y -CONFIG_ELBC_BR3_OR3=y -CONFIG_BR3_OR3_NAME="NAND" -CONFIG_BR3_OR3_BASE=0xE0600000 -CONFIG_BR3_ERRORCHECKING_BOTH=y -CONFIG_BR3_MACHINE_FCM=y -CONFIG_OR3_BCTLD_NOT_ASSERTED=y -CONFIG_OR3_SCY_1=y -CONFIG_OR3_CST_ONE_CLOCK=y -CONFIG_OR3_CHT_TWO_CLOCK=y -CONFIG_OR3_RST_ONE_CLOCK=y -CONFIG_OR3_TRLX_RELAXED=y -CONFIG_OR3_EHTR_8_CYCLE=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSECEP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_8=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_PCI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig deleted file mode 100644 index 3ba15a1eb74b..000000000000 --- a/configs/MPC837XEMDS_SLAVE_defconfig +++ /dev/null @@ -1,143 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_MPC83xx=y -CONFIG_TARGET_MPC837XEMDS=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_6_1=y -CONFIG_CORE_PLL_RATIO_15_1=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_RGMII=y -CONFIG_TSEC2_MODE_RGMII=y -CONFIG_LDP_PIN_MUX_STATE_0=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM_LOWER" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="SDRAM_UPPER" -CONFIG_BAT1_BASE=0x10000000 -CONFIG_BAT1_LENGTH_256_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="IMMR" -CONFIG_BAT2_BASE=0xE0000000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_INHIBITED=y -CONFIG_BAT2_ICACHE_GUARDED=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="BCSR" -CONFIG_BAT3_BASE=0xF8000000 -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_ICACHE_INHIBITED=y -CONFIG_BAT3_ICACHE_GUARDED=y -CONFIG_BAT3_DCACHE_INHIBITED=y -CONFIG_BAT3_DCACHE_GUARDED=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xF8000000 -CONFIG_LBLAW1_NAME="BCSR" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_LBLAW3=y -CONFIG_LBLAW3_BASE=0xE0600000 -CONFIG_LBLAW3_NAME="NAND" -CONFIG_LBLAW3_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="BCSR" -CONFIG_BR1_OR1_BASE=0xF8000000 -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_OR1_XACS_EXTENDED=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_OR1_EAD_EXTRA=y -CONFIG_ELBC_BR3_OR3=y -CONFIG_BR3_OR3_NAME="NAND" -CONFIG_BR3_OR3_BASE=0xE0600000 -CONFIG_BR3_ERRORCHECKING_BOTH=y -CONFIG_BR3_MACHINE_FCM=y -CONFIG_OR3_BCTLD_NOT_ASSERTED=y -CONFIG_OR3_SCY_1=y -CONFIG_OR3_CST_ONE_CLOCK=y -CONFIG_OR3_CHT_TWO_CLOCK=y -CONFIG_OR3_RST_ONE_CLOCK=y -CONFIG_OR3_TRLX_RELAXED=y -CONFIG_OR3_EHTR_8_CYCLE=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSECEP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_8=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" -CONFIG_BOOTDELAY=6 -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_TSEC_ENET=y -# CONFIG_PCI is not set -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig deleted file mode 100644 index 5ca8760b36bb..000000000000 --- a/configs/MPC837XEMDS_defconfig +++ /dev/null @@ -1,166 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFE000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SYS_CLK_FREQ=66000000 -CONFIG_MPC83xx=y -CONFIG_HIGH_BATS=y -CONFIG_TARGET_MPC837XEMDS=y -CONFIG_DDR_MC_CLOCK_MODE_1_1=y -CONFIG_SYSTEM_PLL_FACTOR_6_1=y -CONFIG_CORE_PLL_RATIO_15_1=y -CONFIG_PCI_HOST_MODE_ENABLE=y -CONFIG_PCI_INT_ARBITER1_ENABLE=y -CONFIG_BOOT_MEMORY_SPACE_LOW=y -CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y -CONFIG_TSEC1_MODE_RGMII=y -CONFIG_TSEC2_MODE_RGMII=y -CONFIG_LDP_PIN_MUX_STATE_0=y -CONFIG_BAT0=y -CONFIG_BAT0_NAME="SDRAM_LOWER" -CONFIG_BAT0_BASE=0x00000000 -CONFIG_BAT0_LENGTH_256_MBYTES=y -CONFIG_BAT0_ACCESS_RW=y -CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT0_USER_MODE_VALID=y -CONFIG_BAT0_SUPERVISOR_MODE_VALID=y -CONFIG_BAT1=y -CONFIG_BAT1_NAME="SDRAM_UPPER" -CONFIG_BAT1_BASE=0x10000000 -CONFIG_BAT1_LENGTH_256_MBYTES=y -CONFIG_BAT1_ACCESS_RW=y -CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y -CONFIG_BAT1_USER_MODE_VALID=y -CONFIG_BAT1_SUPERVISOR_MODE_VALID=y -CONFIG_BAT2=y -CONFIG_BAT2_NAME="IMMR" -CONFIG_BAT2_BASE=0xE0000000 -CONFIG_BAT2_LENGTH_8_MBYTES=y -CONFIG_BAT2_ACCESS_RW=y -CONFIG_BAT2_ICACHE_INHIBITED=y -CONFIG_BAT2_ICACHE_GUARDED=y -CONFIG_BAT2_DCACHE_INHIBITED=y -CONFIG_BAT2_DCACHE_GUARDED=y -CONFIG_BAT2_USER_MODE_VALID=y -CONFIG_BAT2_SUPERVISOR_MODE_VALID=y -CONFIG_BAT3=y -CONFIG_BAT3_NAME="BCSR" -CONFIG_BAT3_BASE=0xF8000000 -CONFIG_BAT3_ACCESS_RW=y -CONFIG_BAT3_ICACHE_INHIBITED=y -CONFIG_BAT3_ICACHE_GUARDED=y -CONFIG_BAT3_DCACHE_INHIBITED=y -CONFIG_BAT3_DCACHE_GUARDED=y -CONFIG_BAT3_USER_MODE_VALID=y -CONFIG_BAT3_SUPERVISOR_MODE_VALID=y -CONFIG_BAT4=y -CONFIG_BAT4_NAME="FLASH" -CONFIG_BAT4_BASE=0xFE000000 -CONFIG_BAT4_LENGTH_32_MBYTES=y -CONFIG_BAT4_ACCESS_RW=y -CONFIG_BAT4_ICACHE_MEMORYCOHERENCE=y -CONFIG_BAT4_DCACHE_INHIBITED=y -CONFIG_BAT4_DCACHE_GUARDED=y -CONFIG_BAT4_USER_MODE_VALID=y -CONFIG_BAT4_SUPERVISOR_MODE_VALID=y -CONFIG_BAT5=y -CONFIG_BAT5_NAME="STACK_IN_DCACHE" -CONFIG_BAT5_BASE=0xE6000000 -CONFIG_BAT5_ACCESS_RW=y -CONFIG_BAT5_USER_MODE_VALID=y -CONFIG_BAT5_SUPERVISOR_MODE_VALID=y -CONFIG_LBLAW0=y -CONFIG_LBLAW0_BASE=0xFE000000 -CONFIG_LBLAW0_NAME="FLASH" -CONFIG_LBLAW0_LENGTH_32_MBYTES=y -CONFIG_LBLAW1=y -CONFIG_LBLAW1_BASE=0xF8000000 -CONFIG_LBLAW1_NAME="BCSR" -CONFIG_LBLAW1_LENGTH_32_KBYTES=y -CONFIG_LBLAW3=y -CONFIG_LBLAW3_BASE=0xE0600000 -CONFIG_LBLAW3_NAME="NAND" -CONFIG_LBLAW3_LENGTH_32_KBYTES=y -CONFIG_ELBC_BR0_OR0=y -CONFIG_BR0_OR0_NAME="FLASH" -CONFIG_BR0_OR0_BASE=0xFE000000 -CONFIG_BR0_PORTSIZE_16BIT=y -CONFIG_OR0_AM_32_MBYTES=y -CONFIG_OR0_XAM_SET=y -CONFIG_OR0_SCY_15=y -CONFIG_OR0_CSNT_EARLIER=y -CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y -CONFIG_OR0_XACS_EXTENDED=y -CONFIG_OR0_TRLX_RELAXED=y -CONFIG_OR0_EHTR_8_CYCLE=y -CONFIG_OR0_EAD_EXTRA=y -CONFIG_ELBC_BR1_OR1=y -CONFIG_BR1_OR1_NAME="BCSR" -CONFIG_BR1_OR1_BASE=0xF8000000 -CONFIG_OR1_XAM_SET=y -CONFIG_OR1_SCY_15=y -CONFIG_OR1_CSNT_EARLIER=y -CONFIG_OR1_XACS_EXTENDED=y -CONFIG_OR1_TRLX_RELAXED=y -CONFIG_OR1_EHTR_8_CYCLE=y -CONFIG_OR1_EAD_EXTRA=y -CONFIG_ELBC_BR3_OR3=y -CONFIG_BR3_OR3_NAME="NAND" -CONFIG_BR3_OR3_BASE=0xE0600000 -CONFIG_BR3_ERRORCHECKING_BOTH=y -CONFIG_BR3_MACHINE_FCM=y -CONFIG_OR3_BCTLD_NOT_ASSERTED=y -CONFIG_OR3_SCY_1=y -CONFIG_OR3_CST_ONE_CLOCK=y -CONFIG_OR3_CHT_TWO_CLOCK=y -CONFIG_OR3_RST_ONE_CLOCK=y -CONFIG_OR3_TRLX_RELAXED=y -CONFIG_OR3_EHTR_8_CYCLE=y -CONFIG_HID0_FINAL_EMCP=y -CONFIG_HID0_FINAL_ICE=y -CONFIG_HID2_HBE=y -CONFIG_ACR_PIPE_DEP_4=y -CONFIG_ACR_RPTCNT_4=y -CONFIG_SPCR_TSECEP_3=y -CONFIG_LCRR_DBYP_PLL_BYPASSED=y -CONFIG_LCRR_CLKDIV_8=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=6 -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_ADDR=0xFE080000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -# CONFIG_PCI is not set -CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index a53ff93a6b06..4977fd3662a4 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -173,8 +173,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0); switch (odt_rd_cfg) { case ODT_RD_ONLY_OTHER_DIMM: - if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_ARCH_MPC837X)) { + if (!IS_ENABLED(CONFIG_ARCH_MPC8360)) { debug("%s: odt_rd_cfg value %d invalid.\n", ofnode_get_name(node), odt_rd_cfg); return -EINVAL; @@ -185,8 +184,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_RD_ONLY_OTHER_CS: if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_ARCH_MPC831X) && - !IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_ARCH_MPC837X)) { + !IS_ENABLED(CONFIG_ARCH_MPC8360)) { debug("%s: odt_rd_cfg value %d invalid.\n", ofnode_get_name(node), odt_rd_cfg); return -EINVAL; @@ -204,8 +202,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0); switch (odt_wr_cfg) { case ODT_WR_ONLY_OTHER_DIMM: - if (!IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_ARCH_MPC837X)) { + if (!IS_ENABLED(CONFIG_ARCH_MPC8360)) { debug("%s: odt_wr_cfg value %d invalid.\n", ofnode_get_name(node), odt_wr_cfg); return -EINVAL; @@ -216,8 +213,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) case ODT_WR_ONLY_OTHER_CS: if (!IS_ENABLED(CONFIG_ARCH_MPC830X) && !IS_ENABLED(CONFIG_ARCH_MPC831X) && - !IS_ENABLED(CONFIG_ARCH_MPC8360) && - !IS_ENABLED(CONFIG_ARCH_MPC837X)) { + !IS_ENABLED(CONFIG_ARCH_MPC8360)) { debug("%s: odt_wr_cfg value %d invalid.\n", ofnode_get_name(node), odt_wr_cfg); return -EINVAL; diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h deleted file mode 100644 index c42cb426d859..000000000000 --- a/include/configs/MPC837XEMDS.h +++ /dev/null @@ -1,370 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * Dave Liu daveliu@freescale.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -/* - * IP blocks clock configuration - */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ -#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000000 -#define CONFIG_SYS_SICRL 0x00000000 - -/* - * Output Buffer Impedance - */ -#define CONFIG_SYS_OBIR 0x31100000 - -#define CONFIG_HWCONFIG - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_83XX_DDR_USES_CS0 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x80080001 */ /* ODT 150ohm on SoC */ - -#undef CONFIG_DDR_ECC /* support DDR ECC function */ -#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ - -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ - -#if defined(CONFIG_SPD_EEPROM) -#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ -#else -/* - * Manually set up DDR parameters - * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM - * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 - */ -#define CONFIG_SYS_DDR_SIZE 512 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ - | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ - | CSCONFIG_ROW_BIT_14 \ - | CSCONFIG_COL_BIT_10) - /* 0x80010202 */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00620802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (13 << TIMING_CFG1_REFREC_SHIFT) \ - | (3 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x3935d322 */ -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (6 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x131088c8 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x03E00100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ - | (0x1432 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=3, AL=1 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 -#endif - -/* - * Memory test - */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* - * BCSR on the Local Bus - */ -#define CONFIG_SYS_BCSR 0xF8000000 - /* Access window base at BCSR base */ - -/* - * NAND Flash on the Local Bus - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 - -#define CONFIG_SYS_NAND_BASE 0xE0600000 - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } - -/* - * Config on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#ifndef __ASSEMBLY__ -extern int board_pci_host_broken(void); -#endif -#define CONFIG_PCIE -#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ - -#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#endif /* CONFIG_PCI */ - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC1" -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 3 -#define TSEC1_PHY_ADDR_SGMII 8 -#define TSEC2_PHY_ADDR_SGMII 4 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC1" - -/* SERDES */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 -#define CONFIG_FSL_SERDES2 0xe3100 - -/* - * SATA - */ -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#ifdef CONFIG_FSL_SATA -#define CONFIG_LBA48 -#endif - -/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC_PIN_MUX -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc8379_mds.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index ea67868ea012..d10f442def8a 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -124,8 +124,7 @@ #define SPCR_TSEC2EP 0x00000003 #define SPCR_TSEC2EP_SHIFT (31-31)
-#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC837X) +#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) /* SPCR bits - MPC8308, MPC831x and MPC837X specific */ /* TSEC data priority */ #define SPCR_TSECDP 0x00003000 @@ -278,59 +277,6 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001
-#elif defined(CONFIG_ARCH_MPC837X) -/* SICRL bits - MPC837X specific */ -#define SICRL_USB_A 0xC0000000 -#define SICRL_USB_B 0x30000000 -#define SICRL_USB_B_SD 0x20000000 -#define SICRL_UART 0x0C000000 -#define SICRL_GPIO_A 0x02000000 -#define SICRL_GPIO_B 0x01000000 -#define SICRL_GPIO_C 0x00800000 -#define SICRL_GPIO_D 0x00400000 -#define SICRL_GPIO_E 0x00200000 -#define SICRL_GPIO_F 0x00180000 -#define SICRL_GPIO_G 0x00040000 -#define SICRL_GPIO_H 0x00020000 -#define SICRL_GPIO_I 0x00010000 -#define SICRL_GPIO_J 0x00008000 -#define SICRL_GPIO_K 0x00004000 -#define SICRL_GPIO_L 0x00003000 -#define SICRL_DMA_A 0x00000800 -#define SICRL_DMA_B 0x00000400 -#define SICRL_DMA_C 0x00000200 -#define SICRL_DMA_D 0x00000100 -#define SICRL_DMA_E 0x00000080 -#define SICRL_DMA_F 0x00000040 -#define SICRL_DMA_G 0x00000020 -#define SICRL_DMA_H 0x00000010 -#define SICRL_DMA_I 0x00000008 -#define SICRL_DMA_J 0x00000004 -#define SICRL_LDP_A 0x00000002 -#define SICRL_LDP_B 0x00000001 - -/* SICRH bits - MPC837X specific */ -#define SICRH_DDR 0x80000000 -#define SICRH_TSEC1_A 0x10000000 -#define SICRH_TSEC1_B 0x08000000 -#define SICRH_TSEC2_A 0x00400000 -#define SICRH_TSEC2_B 0x00200000 -#define SICRH_TSEC2_C 0x00100000 -#define SICRH_TSEC2_D 0x00080000 -#define SICRH_TSEC2_E 0x00040000 -#define SICRH_TMR 0x00010000 -#define SICRH_GPIO2_A 0x00008000 -#define SICRH_GPIO2_B 0x00004000 -#define SICRH_GPIO2_C 0x00002000 -#define SICRH_GPIO2_D 0x00001000 -#define SICRH_GPIO2_E 0x00000C00 -#define SICRH_GPIO2_E_SD 0x00000800 -#define SICRH_GPIO2_F 0x00000300 -#define SICRH_GPIO2_G 0x000000C0 -#define SICRH_GPIO2_H 0x00000030 -#define SICRH_SPI 0x00000003 -#define SICRH_SPI_SD 0x00000001 - #elif defined(CONFIG_ARCH_MPC8308) /* SICRL bits - MPC8308 specific */ #define SICRL_SPI_PF0 (0 << 28) @@ -642,15 +588,7 @@ #define HRCWL_SVCOD_DIV_8 0x20000000 #define HRCWL_SVCOD_DIV_1 0x30000000
-#elif defined(CONFIG_ARCH_MPC837X) -#define HRCWL_SVCOD 0x30000000 -#define HRCWL_SVCOD_SHIFT 28 -#define HRCWL_SVCOD_DIV_4 0x00000000 -#define HRCWL_SVCOD_DIV_8 0x10000000 -#define HRCWL_SVCOD_DIV_2 0x20000000 -#define HRCWL_SVCOD_DIV_1 0x30000000 #elif defined(CONFIG_ARCH_MPC8309) - #define HRCWL_CEVCOD 0x000000C0 #define HRCWL_CEVCOD_SHIFT 6 /* @@ -753,15 +691,11 @@ #if defined(CONFIG_ARCH_MPC834X) #define HRCWH_ROM_LOC_PCI2 0x00200000 #endif -#if defined(CONFIG_ARCH_MPC837X) -#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 -#endif #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
-#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC837X) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 @@ -813,8 +747,7 @@ /* * RSR - Reset Status Register */ -#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \ - defined(CONFIG_ARCH_MPC837X) +#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) #define RSR_RSTSRC 0xF0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 28 #else @@ -1027,45 +960,6 @@ #define SCCR_TDMCM_2 0x00000020 #define SCCR_TDMCM_3 0x00000030
-#elif defined(CONFIG_ARCH_MPC837X) -/* SCCR bits - MPC837X specific */ -#define SCCR_TSEC1CM 0xc0000000 -#define SCCR_TSEC1CM_SHIFT 30 -#define SCCR_TSEC1CM_0 0x00000000 -#define SCCR_TSEC1CM_1 0x40000000 -#define SCCR_TSEC1CM_2 0x80000000 -#define SCCR_TSEC1CM_3 0xC0000000 - -#define SCCR_TSEC2CM 0x30000000 -#define SCCR_TSEC2CM_SHIFT 28 -#define SCCR_TSEC2CM_0 0x00000000 -#define SCCR_TSEC2CM_1 0x10000000 -#define SCCR_TSEC2CM_2 0x20000000 -#define SCCR_TSEC2CM_3 0x30000000 - -#define SCCR_SDHCCM 0x0c000000 -#define SCCR_SDHCCM_SHIFT 26 -#define SCCR_SDHCCM_0 0x00000000 -#define SCCR_SDHCCM_1 0x04000000 -#define SCCR_SDHCCM_2 0x08000000 -#define SCCR_SDHCCM_3 0x0c000000 - -#define SCCR_USBDRCM 0x00c00000 -#define SCCR_USBDRCM_SHIFT 22 -#define SCCR_USBDRCM_0 0x00000000 -#define SCCR_USBDRCM_1 0x00400000 -#define SCCR_USBDRCM_2 0x00800000 -#define SCCR_USBDRCM_3 0x00c00000 - -/* All of the four SATA controllers must have the same clock ratio */ -#define SCCR_SATA1CM 0x000000c0 -#define SCCR_SATA1CM_SHIFT 6 -#define SCCR_SATACM 0x000000ff -#define SCCR_SATACM_SHIFT 0 -#define SCCR_SATACM_0 0x00000000 -#define SCCR_SATACM_1 0x00000055 -#define SCCR_SATACM_2 0x000000aa -#define SCCR_SATACM_3 0x000000ff #elif defined(CONFIG_ARCH_MPC8309) /* SCCR bits - MPC8309 specific */ #define SCCR_SDHCCM 0x0c000000 @@ -1124,7 +1018,7 @@ #elif defined(CONFIG_ARCH_MPC832X) #define CSCONFIG_ODT_RD_CFG 0x00400000 #define CSCONFIG_ODT_WR_CFG 0x00040000 -#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X) +#elif defined(CONFIG_ARCH_MPC8360) #define CSCONFIG_ODT_RD_NEVER 0x00000000 #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000