This adds an SFP binding for the processors it is present on. I have only tested this for the LS1046A.
Signed-off-by: Sean Anderson sean.anderson@seco.com ---
arch/arm/dts/fsl-ls1012a.dtsi | 7 +++++++ arch/arm/dts/fsl-ls1043a.dtsi | 7 +++++++ arch/arm/dts/fsl-ls1046a.dtsi | 7 +++++++ arch/arm/dts/ls1021a.dtsi | 7 +++++++ 4 files changed, 28 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 0ea899c7d7..510d863a66 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -34,6 +34,13 @@ #size-cells = <2>; ranges;
+ sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + }; + clockgen: clocking@1ee1000 { compatible = "fsl,ls1012a-clockgen"; reg = <0x0 0x1ee1000 0x0 0x1000>; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 52dc5a9638..13a999f6f4 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -38,6 +38,13 @@ #size-cells = <2>; ranges;
+ sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + }; + clockgen: clocking@1ee1000 { compatible = "fsl,ls1043a-clockgen"; reg = <0x0 0x1ee1000 0x0 0x1000>; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index a60cbf11fc..f7026e16e0 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -37,6 +37,13 @@ #size-cells = <2>; ranges;
+ sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + }; + clockgen: clocking@1ee1000 { compatible = "fsl,ls1046a-clockgen"; reg = <0x0 0x1ee1000 0x0 0x1000>; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 86192cbb7f..1e1b52eab4 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -81,6 +81,13 @@ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; };
+ sfp: efuse@1e80000 { + compatible = "fsl,ls1021a-sfp"; + reg = <0x0 0x1e80000 0x0 0x1000>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1021a-dcfg", "syscon"; reg = <0x1ee0000 0x10000>;