Thank you for the configuration info about the PHY LAN8720 - I have applied the changed you have mentioned but I am not getting anywhere.
I have enabled the debug at fec_mxc.c file, and when I execute the 'ping" command I get the error -22 back, it seems that the problem might be at a higher layer? it times out at the send packet function: I am using u-boot-2013-10
U-Boot 2013.10- (Jan 17 2014 - 12:01:38)
CPU: Freescale i.MX6SOLO rev1.1 at 792 MHz Reset cause: WDOG Board: imx6 Solo DRAM: 256 MiB NAND: 256 MiB MMC: FSL_SDHC: 0 Display: qvga-rgb (320x240) Error: no valid bmp image at 10800000 In: serial Out: serial Err: serial Net: eth_init: fec_probe(bd, -1, 0) @ 02188000 fec_mii_setspeed: mii_speed 00000014 fec_mdio_read: phy: 00 reg:02 val:0x7 fec_mdio_read: phy: 00 reg:03 val:0xc0f1 fec_mii_setspeed: mii_speed 00000014 fec_mdio_read: phy: 00 reg:00 val:0x3000 fec_mdio_write: phy: 00 reg:00 val:0xb000 fec_mdio_read: phy: 00 reg:00 val:0x3000 fec_mdio_read: phy: 00 reg:04 val:0x1e1 fec_mdio_read: phy: 00 reg:00 val:0x3000 FEC [PRIME] Hit any key to stop autoboot: 0 mmc0 is current device
------- mx6s > ping 172.18.2.5 eth_halt: wait for stop regs eth_halt: done fec_mii_setspeed: mii_speed 00000014 fec_open: fec_open(dev) fec_mdio_read: phy: 00 reg:01 val:0x782d fec_mdio_read: phy: 00 reg:01 val:0x782d fec_open:Speed=100 Using FEC device fec_send: status 0x8c00 index 0 ret -22 fec_recv: ievent 0x0 fec_recv: status 0x8000 fec_recv: stop fec_recv: ievent 0x0 fec_recv: status 0x8000 fec_recv: stop fec_recv: ievent 0x0 fec_recv: status 0x8000 fec_recv: stop
static int fec_send(struct eth_device *dev, void *packet, int length)
.... /* * Wait until frame is sent. On each turn of the wait cycle, we must * invalidate data cache to see what's really in RAM. Also, we need * barrier here. */ while (--timeout) { if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR)) break; }
if (!timeout) ret = -EINVAL;
invalidate_dcache_range(addr, addr + size); if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) ret = -EINVAL;
debug("fec_send: status 0x%x index %d ret %i\n", readw(&fec->tbd_base[fec->tbd_index].status), fec->tbd_index, ret);
....
On Thu, Jan 16, 2014 at 9:37 PM, Andy Ng andreas2025@gmail.com wrote:
Dear colleagues,
I have setup a LAN8720 phy for my imx6Solo/DL custom board but no packets coming out. I can see 50MHz going into the phy from the REF_OUT Pin of the SOLO, I can read the phy ID using the u-boot MDIO commands but when I do ftp or ping nothing comes out.
mx6s > mdio list FEC: 0 - SMSC LAN8710/LAN8720 <--> FEC
For this design I am using ENET_ANATOP_ETHERNET_REF_OUT. Have you used LAN8720 in a similar configuration:
The pinmux i have is the following:
/*
- Ethernet PINS for LAN8720
*/ static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), /* LAN8720 PHY Reset */ MX6_PAD_SD4_DAT1__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL), /* Note: The INT is not handled */ MX6_PAD_ENET_REF_CLK__GPIO_1_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
Where ENET_PAT_CTRL is set as:
#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
And the Ethernet configuration in the config file as follows:
/* Ethernet Configuration */ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII #define CONFIG_CMD_NET #define CONFIG_FEC_MXC #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB #define CONFIG_PHY_SMSC
In the board file:
#ifdef CONFIG_FEC_MXC
/*
- Initialise the pins, and reset the PHY
*/ static void setup_iomux_enet(void) { imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
/* Reset LAN8720 PHY */ gpio_direction_output(ETH_PHY_RESET, 1); udelay(150); gpio_set_value(ETH_PHY_RESET, 0); udelay(150); gpio_set_value(ETH_PHY_RESET, 1); udelay(200);}
int enable_fec_anatop_clock(void) { u32 reg = 0; s32 timeout = 100000;
struct anatop_regs __iomem *anatop = (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; reg = readl(&anatop->pll_enet); if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) || (!(reg & BM_ANADIG_PLL_ENET_LOCK))) { reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; writel(reg, &anatop->pll_enet); while (timeout--) { if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) break; } if (timeout < 0) return -ETIMEDOUT; } /* Enable FEC clock */ reg |= BM_ANADIG_PLL_ENET_ENABLE; reg &= ~BM_ANADIG_PLL_ENET_BYPASS; writel(reg, &anatop->pll_enet); return 0;}
int board_eth_init(bd_t *bis) { int ret;
setup_iomux_enet(); ret = cpu_eth_init(bis); if (ret) { printf("FEC MXC: %s:failed\n", __func__); return ret; } return 0;}
static int setup_fec(void) { struct iomuxc_base_regs *iomuxc_regs = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; int ret;
/* set gpr1[21] to select anatop clock */ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK, 1<< 21);
ret = enable_fec_anatop_clock(); if (ret) return ret; return 0;} #endif
int board_late_init(void) { #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif
return 0;}
int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
/* Read the board ID */ /* Setup the FEC clock */#ifdef CONFIG_FEC_MXC setup_fec(); #endif
return 0;}
The clock gating are as: /* set the default clock gate to save power */ DATA 4, CCM_CCGR0, 0x00C03F3F DATA 4, CCM_CCGR1, 0x0030FC03 DATA 4, CCM_CCGR2, 0x0FFFC000 DATA 4, CCM_CCGR3, 0x3FF00000 DATA 4, CCM_CCGR4, 0x00FFF300 DATA 4, CCM_CCGR5, 0x0F0000C3 DATA 4, CCM_CCGR6, 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */ DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ DATA 4, MX6_IOMUXC_GPR6, 0x007F007F DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
/*
- Setup CCM_CCOSR register as follows:
- cko1_en = 1 --> CKO1 enabled
- cko1_div = 111 --> divide by 8
- cko1_sel = 1011 --> ahb_clk_root
- This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
*/ DATA 4, CCM_CCOSR, 0x000000fb
The ethaddr: ethaddr=02:24:08:32:68:08
Any assistance will be very much appreciated. Thank you. A