Yuriy/Stefan-
This is AMCC confirmation about configuration.
Regards,
Olga Buchonina AMCC PowerPC Applications Engineering
-----Original Message----- From: Stefan Roese [mailto:sr@denx.de] Sent: Tuesday, September 23, 2008 4:43 AM To: Yuri Tikhonov Cc: u-boot@lists.denx.de; Prodyut Hazarika; Olga Buchonina Subject: Re: [U-Boot] [PATCH] 440spe MQ initialization
On Tuesday 23 September 2008, Yuri Tikhonov wrote:
BTW, when I said "recommended by AMCC" in the patch description I referred to the following information forwarded to me by Wolfgang Denk
on Tue Mar 18 2008:
Dear Yuri,
here is some additional (and hopefully helpful) information from AMCC
regarding the observed hangs on the katmai board:
If possible, can you please check if you still see the lock up when you program MQ as follows: set value in HB and if you are using LL also as follows: MQ0_CF1H = 0x80001C80 MQ0_CF1L = 0x80001C80 Additionally, make sure that your PLB settings are: PLB0_ACR = 0xDF000000 ( 4 deep read and 2 deep write) PLB1_ACR = 0xDF000000 ( 4 deep read and 2 deep write) Please let me know if this fixes the issue. I also would like to know how you are programming your DMA and how is the traffic is pipelined. Regards, Olga Buchonina AMCC PowerPC Applications Engineering
Understood. I just would like to see an ACK from AMCC on this since they just updated this MQ init code.
Best regards, Stefan
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