From: Keerthy j-keerthy@ti.com
Add the pmic_data for LP873x PMIC which is used to power up dra71x-evm.
Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating the efuse registers only to use OPP_NOM irrespective of any CONFIG_DRA7_<VOLT>_OPP_{NOM,od,high} is defined.
[1] http://www.ti.com/product/DRA718/technicaldocuments
Signed-off-by: Keerthy j-keerthy@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/arch-omap5/clock.h | 8 +++++ arch/arm/include/asm/omap_common.h | 1 + arch/arm/mach-omap2/omap5/hw_data.c | 16 ++++++++++ board/ti/dra7xx/evm.c | 52 +++++++++++++++++++++++++++++++++ 4 files changed, 77 insertions(+)
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index e8b286b..d104ad2 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -324,6 +324,9 @@ /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000
+/* Offset is 0.73V for LP873x */ +#define LP873X_BUCK_BASE_VOLT_UV 730000 + /* TPS659038 */ #define TPS659038_I2C_SLAVE_ADDR 0x58 #define TPS659038_REG_ADDR_SMPS12 0x23 @@ -338,6 +341,11 @@ #define TPS65917_REG_ADDR_SMPS2 0x27 #define TPS65917_REG_ADDR_SMPS3 0x2F
+/* LP873X */ +#define LP873X_I2C_SLAVE_ADDR 0x60 +#define LP873X_REG_ADDR_BUCK0 0x6 +#define LP873X_REG_ADDR_BUCK1 0x7 +#define LP873X_REG_ADDR_LDO1 0xA
/* TPS */ #define TPS62361_I2C_SLAVE_ADDR 0x60 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 00bd9fc..41986ae 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -600,6 +600,7 @@ extern struct omap_sys_ctrl_regs const omap5_ctrl; extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
extern struct pmic_data tps659038; +extern struct pmic_data lp8733;
void hw_data_init(void);
diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index 0674480..8e7480e 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -336,6 +336,22 @@ struct pmic_data tps659038 = { .gpio_en = 0, };
+/* The LP8732 and LP8733 are software-compatible, use common struct */ +struct pmic_data lp8733 = { + .base_offset = LP873X_BUCK_BASE_VOLT_UV, + .step = 5000, /* 5 mV represented in uV */ + /* + * Offset codes 0 - 0x13 Invalid. + * Offset codes 0x14 0x17 give 10mV steps + * Offset codes 0x17 through 0x9D give 5mV steps + * So let us start with our operating range from .73V + */ + .start_code = 0x17, + .i2c_slave_addr = 0x60, + .pmic_bus_init = gpi2c_init, + .pmic_write = palmas_i2c_write_u8, +}; + struct vcores_data omap5430_volts = { .mpu.value[OPP_NOM] = VDD_MPU, .mpu.addr = SMPS_REG_ADDR_12_MPU, diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index b2ca75b..f2a60ae 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -408,10 +408,60 @@ struct vcores_data dra722_volts = { .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, };
+struct vcores_data dra718_volts = { + /* + * In the case of dra71x GPU MPU and CORE + * are all powered up by BUCK0 of LP873X PMIC + */ + .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, + .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = LP873X_REG_ADDR_BUCK0, + .mpu.pmic = &lp8733, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, + + .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, + .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = LP873X_REG_ADDR_BUCK0, + .core.pmic = &lp8733, + + .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, + .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = LP873X_REG_ADDR_BUCK0, + .gpu.pmic = &lp8733, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, + + /* + * The DSPEVE and IVA rails are grouped on DRA71x-evm + * and are powered by BUCK1 of LP873X PMIC + */ + .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, + .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = LP873X_REG_ADDR_BUCK1, + .eve.pmic = &lp8733, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, + + .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, + .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = LP873X_REG_ADDR_BUCK1, + .iva.pmic = &lp8733, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, +}; + int get_voltrail_opp(int rail_offset) { int opp;
+ /* + * DRA71x supports only OPP_NOM. + */ + if (board_is_dra71x_evm()) + return OPP_NOM; + switch (rail_offset) { case VOLT_MPU: opp = DRA7_MPU_OPP; @@ -534,6 +584,8 @@ void vcores_init(void) *omap_vcores = &dra752_volts; } else if (board_is_dra72x_evm()) { *omap_vcores = &dra722_volts; + } else if (board_is_dra71x_evm()) { + *omap_vcores = &dra718_volts; } else { /* If EEPROM is not populated */ if (is_dra72x())