On Thu, 23 Oct 2008, Kyungmin Park wrote:
(1 << 0) - ignored, default 0, so, better set it to 0 | (0 << 1) - set Xm0CSn[2] to OneNANDC CS0 or NFCON CS0 | (1 << 2) - ignored, default 0, so, better set it to 0 | (1 << 3) - set Xm0CSn[3] to SROMC CS3
So, we should just write an 8 in it:
mov r1, #0x8str r1, [r0]
- The comment in the code doesn't look right. According to the above it
should read
/* Xm0CSn[2] = OneNANDC CS0 or NFCON CS0, Xm0CSn[3] = SROMC CS3 */Right, and also add OneNAND & NFCON is depends on XNANDSEL.
In the datasheet this signal is called XSELNAND. And I don't think we have to quote this in the comment. This is a hardware configuration issue, not software, and we are not explaining the complete NAND configuration here, otherwise we would have to mention OM signals too, maybe more.
As you know mem_ctrl_asm_init is common code and other boards can use it without board specific codes.
In OneNAND board, it should be set as 0x1002
Sorry, do not understand what "it." If you mean the MEM_SYS_CFG then I also don't understand this. As I quoted from the datasheet above, bit 1 set to 0 (0 << 1) is for _both_ - NAND or OneNAND. You suggest to set it to 1, which is SROMC CS2. And (1 << 12) is the data bus width, which also doesn't seem to be directly related to the NAND / OneNAND selection. Or did you mean another register?
Thanks Guennadi --- Guennadi Liakhovetski, Ph.D.
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