This patch can be cancel/ignore ... PLL initialization is BOARD-specific and not SoC .... So, now, no more problem about magic number in others boards and management of s3c2410/s3c2440 :).
On Sun, Apr 22, 2012 at 11:32:18PM +0200, Marek Vasut wrote:
Dear Gabriel Huau,
On Sun, Apr 22, 2012 at 10:30:52PM +0200, Marek Vasut wrote:
Dear Gabriel Huau,
Signed-off-by: Gabriel Huau contact@huau-gabriel.fr
arch/arm/cpu/arm920t/s3c24x0/timer.c | 36
++++++++++++++++++++++++++++++++++ board/mpl/vcma9/lowlevel_init.S |
22 --------------------- board/samsung/smdk2410/smdk2410.c | 19
3 files changed, 36 insertions(+), 41 deletions(-)
diff --git a/arch/arm/cpu/arm920t/s3c24x0/timer.c b/arch/arm/cpu/arm920t/s3c24x0/timer.c index d8668be..7ff687c 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/timer.c +++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c @@ -37,8 +37,27 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_S3C2440 +/*
- PLL/Clock configuration
- */
+/* FCLK = 405 MHz, HCLK = 101 MHz, PCLK = 50 MHz, UCLK = 48 MHz */ +#define CLKDIVN_VAL 7 +#define M_MDIV 0x7f +#define M_PDIV 0x2 +#define M_SDIV 0x1
+#define U_M_MDIV 0x38 +#define U_M_PDIV 0x2 +#define U_M_SDIV 0x2 +#endif
So after applying your patch, timer driver won't build for 2410 ?
Yes it will build, This patch is only for s3c2440. I just moved PLL initialization of s3c2440 board to this file. I don't know if theses values are correct for s3c2410 too.
I think these should be unified ... all these #ifdef blocks are stupid
- /* configure MPLL */
- clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
- /* some delay between MPLL and UPLL */
- __udelay(8000);
+#endif
return 0;
}
diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index dadaac7..4deb451 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S
@@ -262,28 +262,6 @@ lowlevel_init: cmp r3, r4 bne 0b
- /* setup MPLL registers */
- ldr r1, =CLKBASE
- ldr r4, =0xFFFFFF
- add r3, r2, #4 /* r3 points to PLL values */
- str r4, [r1, #LOCKTIME]
- ldmia r3, {r4,r5}
- str r5, [r1, #UPLLCON] /* writing PLL register */
/* !! order seems to be important !! */- /* a little delay */
- ldr r3, =0x4000
-0:
- subs r3, r3, #1
- bne 0b
- str r4, [r1, #MPLLCON] /* writing PLL register */
/* !! order seems to be important !! */- /* a little delay */
- ldr r3, =0x4000
-0:
subs r3, r3, #1
bne 0b
/* everything is fine now */ mov pc, lr
diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c index e9ba922..3beb587 100644 --- a/board/samsung/smdk2410/smdk2410.c +++ b/board/samsung/smdk2410/smdk2410.c @@ -69,27 +69,8 @@ static inline void pll_delay(unsigned long loops)
int board_early_init_f(void) {
struct s3c24x0_clock_power * const clk_power =
s3c24x0_get_base_clock_power();struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
writel(0xFFFFFF, &clk_power->locktime);
/* configure MPLL */
writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
&clk_power->mpllcon);/* some delay between MPLL and UPLL */
pll_delay(4000);
/* configure UPLL */
writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
&clk_power->upllcon);/* some delay between MPLL and UPLL */
pll_delay(8000);
/* set up the I/O ports */ writel(0x007FFFFF, &gpio->gpacon); writel(0x00044555, &gpio->gpbcon);
Magic?
I don't maintain theses boards, I just removed PLL initialization because I moved it. So for magic values in I/O port, we have to contact the maintainers :).
Good idea, please do :-)
Best regards, Marek Vasut
Best regards, Marek Vasut