On Sunday, October 12, 2014 at 08:33:21 AM, Sean Cross wrote:
On 12/10/2014 05:04, Fabio Estevam wrote:
On Sat, Oct 11, 2014 at 11:21 AM, Sean Cross xobs@kosagi.com wrote:
Ok, understood. Just curious: which Ethernet PHY is used on the novena board?
It's the same Micrel PHY used on the Sabrelite, the KSZ9021.
nitrogen/sabrelite holds Ethernet PHY reset low for 10ms, which is in accordance with ksz9021 datasheet.
Shouldn't we wait 10ms here as well?
The reference manual for the PHY indicates that you should hold reset low for 10ms after the supply voltage stabilizes. So long as it takes at least 10msto get from the point at which the CPU starts executing its ROM code to the point at which the reset line is toggled, we will be fine.
This definitelly is the case, so I presume we don't need the delay ?
Best regards, Marek Vasut