Hi Wouter,
On Friday 24 July 2009 09:48:17 Wouter Eckhardt wrote:
Yes, I've checked the VxWorks kernel code. The comments mention that if caching is enabled, the cache should be flushed before the call to MMU TLB initialization is done. However, the calling code never actually flushes the cache. So they're not even following their own advice. In the calling code, they just assume that caching is disabled.
OK.
- Is U-Boot reconfiguring the TLBs after init.S has executed?
Yes. But only one (IIRC). The first TLB for bootrom access. Caching will be disabled before relocating to SDRAM.
Hmmm. This should be a problem since I changed the TLB settings to have SDRAM at the first TLB. However, the SDRAM gets remapped in a different TLB as well. Where in the code can I find this? I tried looking for something like that, but couldn't find it. Perhaps that piece of code is actually replacing all TLBs, not just the bootrom access one.
Take a look at Sequoia. It has support for VxWorks booting. You need to switch the sequence of the TLB entries. init.S:
/* vxWorks needs this as first entry for the Machine Check interrupt */ tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
And you need to set CONFIG_SYS_TLB_FOR_BOOT_FLASH in your board config header to the number of the boot TLB entry.
Let me know if this helps.
Best regards, Stefan
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