Do DDR initialization using the procedural mx6_dram_cfg() instead of programming the MMDC using a raw list of register/value pairs, this solves some rare boot failures on specific "bad" modules.
Calibration values, DDR geometry are unchanged, memory timings are updated according to the relevant memory datasheet, no changes on the power consumption.
For IT temperature range SKUs CL is decreased from 8 to 7 and tFAW value is increased, for commercial temperature range SKUs some changes on ODT parameters.
This change was validated over a range of different apalis-imx6 SoM, on the whole working temperature range with weeks of continuous testing.
Signed-off-by: Francesco Dolcini francesco.dolcini@toradex.com --- board/toradex/apalis_imx6/apalis_imx6.c | 442 ++++++++++-------------- 1 file changed, 187 insertions(+), 255 deletions(-)
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 5604c4646cff..c6f3092ac41e 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -771,244 +771,6 @@ void ldo_mode_set(int ldo_bypass) #include "asm/arch/iomux.h" #include "asm/arch/crm_regs.h"
-static int mx6_com_dcd_table[] = { -/* ddr-setup.cfg */ -MX6_IOM_DRAM_SDQS0, 0x00000030, -MX6_IOM_DRAM_SDQS1, 0x00000030, -MX6_IOM_DRAM_SDQS2, 0x00000030, -MX6_IOM_DRAM_SDQS3, 0x00000030, -MX6_IOM_DRAM_SDQS4, 0x00000030, -MX6_IOM_DRAM_SDQS5, 0x00000030, -MX6_IOM_DRAM_SDQS6, 0x00000030, -MX6_IOM_DRAM_SDQS7, 0x00000030, - -MX6_IOM_GRP_B0DS, 0x00000030, -MX6_IOM_GRP_B1DS, 0x00000030, -MX6_IOM_GRP_B2DS, 0x00000030, -MX6_IOM_GRP_B3DS, 0x00000030, -MX6_IOM_GRP_B4DS, 0x00000030, -MX6_IOM_GRP_B5DS, 0x00000030, -MX6_IOM_GRP_B6DS, 0x00000030, -MX6_IOM_GRP_B7DS, 0x00000030, -MX6_IOM_GRP_ADDDS, 0x00000030, -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -MX6_IOM_GRP_CTLDS, 0x00000030, - -MX6_IOM_DRAM_DQM0, 0x00020030, -MX6_IOM_DRAM_DQM1, 0x00020030, -MX6_IOM_DRAM_DQM2, 0x00020030, -MX6_IOM_DRAM_DQM3, 0x00020030, -MX6_IOM_DRAM_DQM4, 0x00020030, -MX6_IOM_DRAM_DQM5, 0x00020030, -MX6_IOM_DRAM_DQM6, 0x00020030, -MX6_IOM_DRAM_DQM7, 0x00020030, - -MX6_IOM_DRAM_CAS, 0x00020030, -MX6_IOM_DRAM_RAS, 0x00020030, -MX6_IOM_DRAM_SDCLK_0, 0x00020030, -MX6_IOM_DRAM_SDCLK_1, 0x00020030, - -MX6_IOM_DRAM_RESET, 0x00020030, -MX6_IOM_DRAM_SDCKE0, 0x00003000, -MX6_IOM_DRAM_SDCKE1, 0x00003000, - -MX6_IOM_DRAM_SDODT0, 0x00003030, -MX6_IOM_DRAM_SDODT1, 0x00003030, - -/* (differential input) */ -MX6_IOM_DDRMODE_CTL, 0x00020000, -/* (differential input) */ -MX6_IOM_GRP_DDRMODE, 0x00020000, -/* disable ddr pullups */ -MX6_IOM_GRP_DDRPKE, 0x00000000, -MX6_IOM_DRAM_SDBA2, 0x00000000, -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -MX6_IOM_GRP_DDR_TYPE, 0x000C0000, - -/* Read data DQ Byte0-3 delay */ -MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333, -MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333, -MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333, -MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, - -/* - * MDMISC mirroring interleaved (row/bank/col) - */ -MX6_MMDC_P0_MDMISC, 0x00081740, - -/* - * MDSCR con_req - */ -MX6_MMDC_P0_MDSCR, 0x00008000, - -/* 1066mhz_4x128mx16.cfg */ - -MX6_MMDC_P0_MDPDC, 0x00020036, -MX6_MMDC_P0_MDCFG0, 0x555A7954, -MX6_MMDC_P0_MDCFG1, 0xDB328F64, -MX6_MMDC_P0_MDCFG2, 0x01FF00DB, -MX6_MMDC_P0_MDRWD, 0x000026D2, -MX6_MMDC_P0_MDOR, 0x005A1023, -MX6_MMDC_P0_MDOTC, 0x09555050, -MX6_MMDC_P0_MDPDC, 0x00025576, -MX6_MMDC_P0_MDASP, 0x00000027, -MX6_MMDC_P0_MDCTL, 0x831A0000, -MX6_MMDC_P0_MDSCR, 0x04088032, -MX6_MMDC_P0_MDSCR, 0x00008033, -MX6_MMDC_P0_MDSCR, 0x00428031, -MX6_MMDC_P0_MDSCR, 0x19308030, -MX6_MMDC_P0_MDSCR, 0x04008040, -MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003, -MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003, -MX6_MMDC_P0_MDREF, 0x00005800, -MX6_MMDC_P0_MPODTCTRL, 0x00000000, -MX6_MMDC_P1_MPODTCTRL, 0x00000000, - -MX6_MMDC_P0_MPDGCTRL0, 0x432A0338, -MX6_MMDC_P0_MPDGCTRL1, 0x03260324, -MX6_MMDC_P1_MPDGCTRL0, 0x43340344, -MX6_MMDC_P1_MPDGCTRL1, 0x031E027C, - -MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E, -MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37, - -MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C, -MX6_MMDC_P1_MPWRDLCTL, 0x4336453F, - -MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E, -MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B, -MX6_MMDC_P1_MPWLDECTRL0, 0x00060015, -MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E, - -MX6_MMDC_P0_MPMUR0, 0x00000800, -MX6_MMDC_P1_MPMUR0, 0x00000800, -MX6_MMDC_P0_MDSCR, 0x00000000, -MX6_MMDC_P0_MAPSR, 0x00011006, -}; - -static int mx6_it_dcd_table[] = { -/* ddr-setup.cfg */ -MX6_IOM_DRAM_SDQS0, 0x00000030, -MX6_IOM_DRAM_SDQS1, 0x00000030, -MX6_IOM_DRAM_SDQS2, 0x00000030, -MX6_IOM_DRAM_SDQS3, 0x00000030, -MX6_IOM_DRAM_SDQS4, 0x00000030, -MX6_IOM_DRAM_SDQS5, 0x00000030, -MX6_IOM_DRAM_SDQS6, 0x00000030, -MX6_IOM_DRAM_SDQS7, 0x00000030, - -MX6_IOM_GRP_B0DS, 0x00000030, -MX6_IOM_GRP_B1DS, 0x00000030, -MX6_IOM_GRP_B2DS, 0x00000030, -MX6_IOM_GRP_B3DS, 0x00000030, -MX6_IOM_GRP_B4DS, 0x00000030, -MX6_IOM_GRP_B5DS, 0x00000030, -MX6_IOM_GRP_B6DS, 0x00000030, -MX6_IOM_GRP_B7DS, 0x00000030, -MX6_IOM_GRP_ADDDS, 0x00000030, -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -MX6_IOM_GRP_CTLDS, 0x00000030, - -MX6_IOM_DRAM_DQM0, 0x00020030, -MX6_IOM_DRAM_DQM1, 0x00020030, -MX6_IOM_DRAM_DQM2, 0x00020030, -MX6_IOM_DRAM_DQM3, 0x00020030, -MX6_IOM_DRAM_DQM4, 0x00020030, -MX6_IOM_DRAM_DQM5, 0x00020030, -MX6_IOM_DRAM_DQM6, 0x00020030, -MX6_IOM_DRAM_DQM7, 0x00020030, - -MX6_IOM_DRAM_CAS, 0x00020030, -MX6_IOM_DRAM_RAS, 0x00020030, -MX6_IOM_DRAM_SDCLK_0, 0x00020030, -MX6_IOM_DRAM_SDCLK_1, 0x00020030, - -MX6_IOM_DRAM_RESET, 0x00020030, -MX6_IOM_DRAM_SDCKE0, 0x00003000, -MX6_IOM_DRAM_SDCKE1, 0x00003000, - -MX6_IOM_DRAM_SDODT0, 0x00003030, -MX6_IOM_DRAM_SDODT1, 0x00003030, - -/* (differential input) */ -MX6_IOM_DDRMODE_CTL, 0x00020000, -/* (differential input) */ -MX6_IOM_GRP_DDRMODE, 0x00020000, -/* disable ddr pullups */ -MX6_IOM_GRP_DDRPKE, 0x00000000, -MX6_IOM_DRAM_SDBA2, 0x00000000, -/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ -MX6_IOM_GRP_DDR_TYPE, 0x000C0000, - -/* Read data DQ Byte0-3 delay */ -MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333, -MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333, -MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333, -MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333, -MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333, - -/* - * MDMISC mirroring interleaved (row/bank/col) - */ -MX6_MMDC_P0_MDMISC, 0x00081740, - -/* - * MDSCR con_req - */ -MX6_MMDC_P0_MDSCR, 0x00008000, - -/* 1066mhz_4x256mx16.cfg */ - -MX6_MMDC_P0_MDPDC, 0x00020036, -MX6_MMDC_P0_MDCFG0, 0x898E78f5, -MX6_MMDC_P0_MDCFG1, 0xff328f64, -MX6_MMDC_P0_MDCFG2, 0x01FF00DB, -MX6_MMDC_P0_MDRWD, 0x000026D2, -MX6_MMDC_P0_MDOR, 0x008E1023, -MX6_MMDC_P0_MDOTC, 0x09444040, -MX6_MMDC_P0_MDPDC, 0x00025576, -MX6_MMDC_P0_MDASP, 0x00000047, -MX6_MMDC_P0_MDCTL, 0x841A0000, -MX6_MMDC_P0_MDSCR, 0x02888032, -MX6_MMDC_P0_MDSCR, 0x00008033, -MX6_MMDC_P0_MDSCR, 0x00048031, -MX6_MMDC_P0_MDSCR, 0x19408030, -MX6_MMDC_P0_MDSCR, 0x04008040, -MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003, -MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003, -MX6_MMDC_P0_MDREF, 0x00007800, -MX6_MMDC_P0_MPODTCTRL, 0x00022227, -MX6_MMDC_P1_MPODTCTRL, 0x00022227, - -MX6_MMDC_P0_MPDGCTRL0, 0x03300338, -MX6_MMDC_P0_MPDGCTRL1, 0x03240324, -MX6_MMDC_P1_MPDGCTRL0, 0x03440350, -MX6_MMDC_P1_MPDGCTRL1, 0x032C0308, - -MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E, -MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46, - -MX6_MMDC_P0_MPWRDLCTL, 0x403E463E, -MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46, - -MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E, -MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B, -MX6_MMDC_P1_MPWLDECTRL0, 0x00060015, -MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E, - -MX6_MMDC_P0_MPMUR0, 0x00000800, -MX6_MMDC_P1_MPMUR0, 0x00000800, -MX6_MMDC_P0_MDSCR, 0x00000000, -MX6_MMDC_P0_MAPSR, 0x00011006, -}; - static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -1033,27 +795,185 @@ static void ccgr_init(void) writel(0x000000FB, &ccm->ccosr); }
-static void ddr_init(int *table, int size) -{ - int i;
- for (i = 0; i < size / 2 ; i++) - writel(table[2 * i + 1], table[2 * i]); -} +#define PAD_CTL_INPUT_DDR BIT(17) + +struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + /* Differential input, 40 ohm DSE */ + .dram_sdclk_0 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR, + .dram_sdclk_1 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR, + .dram_cas = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR, + .dram_ras = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR, + .dram_reset = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR, + + /* SDKE[0:1]: BIT(12) and BIT(13) are reserved and set at reset */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + + .dram_sdba2 = 0x00000000, + + /* ODT[0:1]: 40 ohm DSE, BIT(12) and BIT(13) are reserved and set at reset */ + .dram_sdodt0 = PAD_CTL_DSE_40ohm | 0x00003000, + .dram_sdodt1 = PAD_CTL_DSE_40ohm | 0x00003000, + + /* SDQS[0:7]: 40 ohm DSE, Pull/Keeper Disabled, ODT Disabled */ + .dram_sdqs0 = PAD_CTL_DSE_40ohm, + .dram_sdqs1 = PAD_CTL_DSE_40ohm, + .dram_sdqs2 = PAD_CTL_DSE_40ohm, + .dram_sdqs3 = PAD_CTL_DSE_40ohm, + .dram_sdqs4 = PAD_CTL_DSE_40ohm, + .dram_sdqs5 = PAD_CTL_DSE_40ohm, + .dram_sdqs6 = PAD_CTL_DSE_40ohm, + .dram_sdqs7 = PAD_CTL_DSE_40ohm, + + /* DQM[0:7]: Differential input, 40 ohm DSE, Pull/Keeper Disabled, ODT Disabled */ + .dram_dqm0 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR, + .dram_dqm1 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR, + .dram_dqm2 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR, + .dram_dqm3 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR, + .dram_dqm4 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR, + .dram_dqm5 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR, + .dram_dqm6 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR, + .dram_dqm7 = PAD_CTL_DSE_40ohm | PAD_CTL_INPUT_DDR, +}; + +struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000C0000, + + /* SDQS[0:7]: Differential input */ + .grp_ddrmode_ctl = PAD_CTL_INPUT_DDR, + + /* DATA[0:63]: Pull/Keeper disabled */ + .grp_ddrpke = 0, + + /* ADDR[0:16], SDBA[0:1]: 40 ohm DSE */ + .grp_addds = PAD_CTL_DSE_40ohm, + + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm DSE */ + .grp_ctlds = PAD_CTL_DSE_40ohm, + + /* DATA[0:63]: Differential input */ + .grp_ddrmode = PAD_CTL_INPUT_DDR, + + /* DATA[0:63]: 40 ohm DSE */ + .grp_b0ds = PAD_CTL_DSE_40ohm, + .grp_b1ds = PAD_CTL_DSE_40ohm, + .grp_b2ds = PAD_CTL_DSE_40ohm, + .grp_b3ds = PAD_CTL_DSE_40ohm, + .grp_b4ds = PAD_CTL_DSE_40ohm, + .grp_b5ds = PAD_CTL_DSE_40ohm, + .grp_b6ds = PAD_CTL_DSE_40ohm, + .grp_b7ds = PAD_CTL_DSE_40ohm, +}; + +struct mx6_ddr_sysinfo sysinfo = { + .dsize = 2, /* width of data bus: 2=64 */ + .cs_density = 32, /* full range so that get_mem_size() works, 32Gb per CS */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, /* Dynamic ODT, RZQ/2 */ + .rtt_nom = 0, /* Disabled */ + .walat = 0, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .pd_fast_exit = 1, /* enable precharge power-down fast exit */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 3, /* 4 refresh commands per refresh cycle */ +}; + +static const struct mx6_mmdc_calibration mx6_mmdc_calib = { + .p0_mpwldectrl0 = 0x0009000E, + .p0_mpwldectrl1 = 0x0018000B, + .p1_mpwldectrl0 = 0x00060015, + .p1_mpwldectrl1 = 0x0006000E, + .p0_mpdgctrl0 = 0x432A0338, + .p0_mpdgctrl1 = 0x03260324, + .p1_mpdgctrl0 = 0x43340344, + .p1_mpdgctrl1 = 0x031E027C, + .p0_mprddlctl = 0x33272D2E, + .p1_mprddlctl = 0x2F312B37, + .p0_mpwrdlctl = 0x3A35433C, + .p1_mpwrdlctl = 0x4336453F, +}; + +static const struct mx6_ddr3_cfg ddr3_cfg = { + .mem_speed = 1066, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1312, + .trcmin = 4812, + .trasmin = 3500, + .SRT = 0, +}; + +struct mx6_ddr_sysinfo sysinfo_it = { + .dsize = 2, /* width of data bus: 2=64 */ + .cs_density = 32, /* full range so that get_mem_size() works, 32Gb per CS */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1, /* Dynamic ODT, RZQ/4 */ + .rtt_nom = 1, /* RZQ/4 */ + .walat = 0, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .pd_fast_exit = 1, /* enable precharge power-down fast exit */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ +}; + +static const struct mx6_mmdc_calibration mx6_mmdc_calib_it = { + .p0_mpwldectrl0 = 0x0009000E, + .p0_mpwldectrl1 = 0x0018000B, + .p1_mpwldectrl0 = 0x00060015, + .p1_mpwldectrl1 = 0x0006000E, + .p0_mpdgctrl0 = 0x03300338, + .p0_mpdgctrl1 = 0x03240324, + .p1_mpdgctrl0 = 0x03440350, + .p1_mpdgctrl1 = 0x032C0308, + .p0_mprddlctl = 0x40363C3E, + .p1_mprddlctl = 0x3C3E3C46, + .p0_mpwrdlctl = 0x403E463E, + .p1_mpwrdlctl = 0x4A384C46, +}; + +static const struct mx6_ddr3_cfg ddr3_cfg_it = { + .mem_speed = 1066, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1312, + .trcmin = 4812, + .trasmin = 3500, + .SRT = 1, +}; +
/* Perform DDR DRAM calibration */ -static void spl_dram_perform_cal(void) +static void spl_dram_perform_cal(const struct mx6_ddr_sysinfo *ddr_sysinfo) { #ifdef CONFIG_MX6_DDRCAL int err; - struct mx6_ddr_sysinfo ddr_sysinfo = { - .dsize = 2, - };
- err = mmdc_do_write_level_calibration(&ddr_sysinfo); + err = mmdc_do_write_level_calibration(ddr_sysinfo); if (err) printf("error %d from write level calibration\n", err); - err = mmdc_do_dqs_calibration(&ddr_sysinfo); + err = mmdc_do_dqs_calibration(ddr_sysinfo); if (err) printf("error %d from dqs calibration\n", err); #endif @@ -1061,23 +981,35 @@ static void spl_dram_perform_cal(void)
static void spl_dram_init(void) { - int minc, maxc; + bool temp_grade_it;
- switch (get_cpu_temp_grade(&minc, &maxc)) { + switch (get_cpu_temp_grade(NULL, NULL)) { case TEMP_COMMERCIAL: case TEMP_EXTCOMMERCIAL: puts("Commercial temperature grade DDR3 timings.\n"); - ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table)); + temp_grade_it = false; break; case TEMP_INDUSTRIAL: case TEMP_AUTOMOTIVE: default: puts("Industrial temperature grade DDR3 timings.\n"); - ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table)); + temp_grade_it = true; break; }; + + mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); + + if (temp_grade_it) + mx6_dram_cfg(&sysinfo_it, &mx6_mmdc_calib_it, &ddr3_cfg_it); + else + mx6_dram_cfg(&sysinfo, &mx6_mmdc_calib, &ddr3_cfg); + udelay(100); - spl_dram_perform_cal(); + + if (temp_grade_it) + spl_dram_perform_cal(&sysinfo_it); + else + spl_dram_perform_cal(&sysinfo); }
void board_init_f(ulong dummy)