On Wed, 27 Apr 2022 15:31:24 -0500 Samuel Holland samuel@sholland.org wrote:
Hi,
Copy the devicetree source for the A10s/A13/GR8, A31(s), and A23/A33/R16 SoCs and all existing boards from the Linux v5.18-rc1 tag.
These changes are combined into one commit due to interdependencies:
- The unit addresses were removed from bitbanged I2C buses, which drives a Kconfig default change. This affects sun5i-a13-utoo-p66.dts and sun6i-a31-colombus.dts.
- The pinctrl nodes were renamed, including some used by the shared header sunxi-reference-design-tablet.dtsi.
To maintain ABI compatibility with existing LTS kernels, one change moving some IP blocks to the r_intc interrupt controller is excluded. This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.
This commit renames the file sun8i-r16-nintendo-nes-classic-edition.dts to sun8i-r16-nintendo-nes-classic.dts to match the Linux tree.
This commit also adds the following new board devicetrees:
- sun5i-a13-licheepi-one.dts
- sun5i-a13-pocketbook-touch-lux-3.dts
- sun5i-gr8-evb.dts
- sun8i-a23-ippo-q8h-v1.2.dts
- sun8i-a23-ippo-q8h-v5.dts
- sun8i-a33-et-q8-v1.6.dts
- sun8i-a33-ippo-q8h-v1.2.dts
- sun8i-r16-nintendo-super-nes-classic.dts
As with the other SoCs, updates of note are conversion of GPIO pull-up from pinconf to GPIO flags and renaming the detection GPIO properties in the USB PHY nodes.
Signed-off-by: Samuel Holland samuel@sholland.org
So that's a big one. The sync part looks good, I compared the files against the kernel, and the r_intc change is the only difference.
Most of the changes are about node names and GPIO / pinctrl usage, which *should* be fine, especially for U-Boot.
However there are a number of incompatible changes, I marked them below in the patch, for reference, but enumerate them here for easier discussion:
- "allwinner,sun4i-a10-sram-controller" got replaced with "allwinner,sun5i-a13-system-control", in sun5i-a13.dtsi. U-Boot doesn't care, and the Linux driver interestingly doesn't make a difference. So not sure why the new name wasn't just *added*. This would affect pre v4.19 kernels, only, so I wouldn't consider this a real problem.
- "urt,umsh-8596md-t", "simple-panel" was changed to "bananapi,s070wv20-ct16", in sun5i-a13-q8-tablet.dts. I think U-Boot shouldn't be affected, as panel usage is controlled via Kconfig. For the kernel it seems to be v4.20 adding support.
- A23/A33 suffer from a change in the timer compatible string (in sun8i-a23-a33.dtsi), requiring Linux v5.4 at least. I am not sure how fatal this is, since we have the arch timer in those SoCs.
- More problematic seems to be the rtc compatible string change in sun8i-a23-a33.dtsi, which restricts kernel compatibility to v5.0 and later. I am not sure if that prevents the CCU and pinctrl to probe (because they use the first rtc provided clock as one of their input clocks). I wonder if having the old compatible string as a fallback is feasible: I don't the second RTC clock used anywhere, and the RTC/clock driver doesn't seem to make a difference between the two compatibles otherwise.
So overall this might look bad, but the breakages are: a) only for those older generation of devices, which probably don't use UEFI boot or otherwise rely on $fdtcontroladdr for the kernel, and b) will probably work fine with kernel v5.4 onwards, which seems to be reasonably old and well spread by now.
So for the sake of getting our DTs much closer to the kernel copy, I am happy with this change.
Reviewed-by: Andre Przywara andre.przywara@arm.com
Cheers, Andre
arch/arm/dts/Makefile | 10 +- arch/arm/dts/axp22x.dtsi | 11 +- arch/arm/dts/sun5i-a10s-auxtek-t003.dts | 16 +- arch/arm/dts/sun5i-a10s-auxtek-t004.dts | 35 +- arch/arm/dts/sun5i-a10s-mk802.dts | 31 +- arch/arm/dts/sun5i-a10s-olinuxino-micro.dts | 68 +--- arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts | 22 +- arch/arm/dts/sun5i-a10s-wobo-i5.dts | 34 +- arch/arm/dts/sun5i-a10s.dtsi | 30 +- arch/arm/dts/sun5i-a13-ampe-a76.dts | 2 +- .../dts/sun5i-a13-empire-electronix-d709.dts | 41 +-- arch/arm/dts/sun5i-a13-hsg-h702.dts | 37 +- arch/arm/dts/sun5i-a13-inet-86vs.dts | 2 +- arch/arm/dts/sun5i-a13-licheepi-one.dts | 214 +++++++++++ arch/arm/dts/sun5i-a13-olinuxino-micro.dts | 50 +-- arch/arm/dts/sun5i-a13-olinuxino.dts | 56 +-- .../dts/sun5i-a13-pocketbook-touch-lux-3.dts | 258 ++++++++++++++ arch/arm/dts/sun5i-a13-q8-tablet.dts | 18 +- arch/arm/dts/sun5i-a13-utoo-p66.dts | 26 +- arch/arm/dts/sun5i-a13.dtsi | 23 +- arch/arm/dts/sun5i-gr8-chip-pro.dts | 38 +- arch/arm/dts/sun5i-gr8-evb.dts | 333 ++++++++++++++++++ arch/arm/dts/sun5i-gr8.dtsi | 12 +- arch/arm/dts/sun5i-r8-chip.dts | 52 +-- .../dts/sun5i-reference-design-tablet.dtsi | 57 +-- arch/arm/dts/sun5i.dtsi | 209 +++++++---- arch/arm/dts/sun6i-a31-app4-evb1.dts | 10 +- arch/arm/dts/sun6i-a31-colombus.dts | 57 +-- arch/arm/dts/sun6i-a31-hummingbird.dts | 75 +--- arch/arm/dts/sun6i-a31-i7.dts | 47 +-- arch/arm/dts/sun6i-a31-m9.dts | 46 +-- arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts | 46 +-- arch/arm/dts/sun6i-a31-mixtile-loftq.dts | 6 +- arch/arm/dts/sun6i-a31.dtsi | 218 +++++++----- arch/arm/dts/sun6i-a31s-colorfly-e708-q1.dts | 2 +- arch/arm/dts/sun6i-a31s-cs908.dts | 17 +- arch/arm/dts/sun6i-a31s-inet-q972.dts | 8 +- arch/arm/dts/sun6i-a31s-primo81.dts | 32 +- arch/arm/dts/sun6i-a31s-sina31s-core.dtsi | 4 +- arch/arm/dts/sun6i-a31s-sina31s.dts | 39 +- arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 144 +++++--- .../sun6i-a31s-yones-toptech-bs1078-v2.dts | 22 +- .../dts/sun6i-reference-design-tablet.dtsi | 22 +- arch/arm/dts/sun8i-a23-a33.dtsi | 308 ++++++++++++---- arch/arm/dts/sun8i-a23-evb.dts | 20 +- arch/arm/dts/sun8i-a23-gt90h-v4.dts | 2 +- arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts | 73 ++++ arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts | 73 ++++ .../dts/sun8i-a23-polaroid-mid2407pxe03.dts | 15 +- .../dts/sun8i-a23-polaroid-mid2809pxe04.dts | 15 +- arch/arm/dts/sun8i-a23-q8-tablet.dts | 10 + arch/arm/dts/sun8i-a23.dtsi | 26 +- ...c-edition.dts => sun8i-a33-et-q8-v1.6.dts} | 32 +- arch/arm/dts/sun8i-a33-ga10h-v1.1.dts | 4 +- arch/arm/dts/sun8i-a33-inet-d978-rev2.dts | 14 +- arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts | 57 +++ arch/arm/dts/sun8i-a33-olinuxino.dts | 12 +- arch/arm/dts/sun8i-a33-q8-tablet.dts | 7 + arch/arm/dts/sun8i-a33-sinlinx-sina33.dts | 34 +- arch/arm/dts/sun8i-a33.dtsi | 270 +++++--------- arch/arm/dts/sun8i-q8-common.dtsi | 31 +- arch/arm/dts/sun8i-r16-bananapi-m2m.dts | 55 ++- .../dts/sun8i-r16-nintendo-nes-classic.dts | 54 +++ .../sun8i-r16-nintendo-super-nes-classic.dts | 11 + arch/arm/dts/sun8i-r16-parrot.dts | 62 +--- .../dts/sun8i-reference-design-tablet.dtsi | 33 +- arch/arm/dts/sunxi-common-regulators.dtsi | 39 -- .../dts/sunxi-reference-design-tablet.dtsi | 11 +- arch/arm/mach-sunxi/Kconfig | 2 +- .../Nintendo_NES_Classic_Edition_defconfig | 2 +- 70 files changed, 2149 insertions(+), 1603 deletions(-) create mode 100644 arch/arm/dts/sun5i-a13-licheepi-one.dts create mode 100644 arch/arm/dts/sun5i-a13-pocketbook-touch-lux-3.dts create mode 100644 arch/arm/dts/sun5i-gr8-evb.dts create mode 100644 arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts create mode 100644 arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts rename arch/arm/dts/{sun8i-r16-nintendo-nes-classic-edition.dts => sun8i-a33-et-q8-v1.6.dts} (81%) create mode 100644 arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts create mode 100644 arch/arm/dts/sun8i-r16-nintendo-nes-classic.dts create mode 100644 arch/arm/dts/sun8i-r16-nintendo-super-nes-classic.dts
...
diff --git a/arch/arm/dts/sun5i-a13-q8-tablet.dts b/arch/arm/dts/sun5i-a13-q8-tablet.dts index a89f29fa3e..f9fc1c8b60 100644 --- a/arch/arm/dts/sun5i-a13-q8-tablet.dts +++ b/arch/arm/dts/sun5i-a13-q8-tablet.dts @@ -49,19 +49,13 @@ compatible = "allwinner,q8-a13", "allwinner,sun5i-a13";
panel: panel {
compatible = "urt,umsh-8596md-t", "simple-panel";#address-cells = <1>;#size-cells = <0>;
compatible = "bananapi,s070wv20-ct16";
This drops the "simple-panel" fallback compatible, and replaces it just a device specific one. This means you need at least Linux v4.20 to use the display.
power-supply = <®_vcc3v3>;enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */backlight = <&backlight>;
port@0 {reg = <0>;/* TODO: lcd panel uses axp gpio0 as enable pin */backlight = <&backlight>;#address-cells = <1>;#size-cells = <0>;panel_input: endpoint@0 {reg = <0>;
port {panel_input: endpoint { remote-endpoint = <&tcon0_out_lcd>; };
[ ... ]
diff --git a/arch/arm/dts/sun5i.dtsi b/arch/arm/dts/sun5i.dtsi index 07f2248ed5..250d6b87ab 100644 --- a/arch/arm/dts/sun5i.dtsi +++ b/arch/arm/dts/sun5i.dtsi @@ -42,14 +42,14 @@
OTHER DEALINGS IN THE SOFTWARE.*/
-#include "skeleton.dtsi"
#include <dt-bindings/clock/sun5i-ccu.h> #include <dt-bindings/dma/sun4i-a10.h> #include <dt-bindings/reset/sun5i-ccu.h>
/ { interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
cpus { #address-cells = <1>;
@@ -68,7 +68,7 @@ #size-cells = <1>; ranges;
framebuffer@0 {
framebuffer-lcd0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0";@@ -77,7 +77,7 @@ status = "disabled"; };
framebuffer@1 {
framebuffer-lcd0-tve0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0";@@ -93,14 +93,14 @@ #size-cells = <1>; ranges;
osc24M: clk@1c20050 {
osc24M: clk-24M { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "osc24M";
osc32k: clk@0 {
osc32k: clk-32k { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>;@@ -108,14 +108,30 @@ }; };
- soc@1c00000 {
- reserved-memory {
#address-cells = <1>;#size-cells = <1>;ranges;/* Address must be kept in the lower 256 MiBs of DRAM for VE. */default-pool {compatible = "shared-dma-pool";size = <0x6000000>;alloc-ranges = <0x40000000 0x10000000>;reusable;linux,cma-default;};- };
- soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>;
dma-ranges;
sram-controller@1c00000 {compatible = "allwinner,sun4i-a10-sram-controller";
system-control@1c00000 {compatible = "allwinner,sun5i-a13-system-control";
This is a change in the compatible string. Linux kernels before v4.19 won't have a driver matching this new string, so will fail to use that device. This would affect USB OTG and EMAC operation.
reg = <0x01c00000 0x30>; #address-cells = <1>; #size-cells = <1>;@@ -127,12 +143,13 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x00000000 0xc000>;
};emac_sram: sram-section@8000 {compatible = "allwinner,sun4i-a10-sram-a3-a4";reg = <0x8000 0x4000>;status = "disabled";
emac_sram: sram-section@8000 {compatible = "allwinner,sun5i-a13-sram-a3-a4","allwinner,sun4i-a10-sram-a3-a4";reg = <0x8000 0x4000>;status = "disabled";}; }; sram_d: sram@10000 {
[ ... ]
diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi index 44f3cad3de..a42fac676b 100644 --- a/arch/arm/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/dts/sun8i-a23-a33.dtsi @@ -42,8 +42,6 @@
OTHER DEALINGS IN THE SOFTWARE.*/
-#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h> @@ -51,13 +49,15 @@
/ { interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
chosen { #address-cells = <1>; #size-cells = <1>; ranges;
simplefb_lcd: framebuffer@0 {
simplefb_lcd: framebuffer-lcd0 { compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0";@@ -68,6 +68,12 @@ }; };
- de: display-engine {
/* compatible gets set in SoC specific dtsi file */allwinner,pipelines = <&fe0>;status = "disabled";- };
- timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -118,12 +124,34 @@ }; };
- soc@1c00000 {
soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges;
system-control@1c00000 {compatible = "allwinner,sun8i-a23-system-control";reg = <0x01c00000 0x30>;#address-cells = <1>;#size-cells = <1>;ranges;sram_c: sram@1d00000 {compatible = "mmio-sram";reg = <0x01d00000 0x80000>;#address-cells = <1>;#size-cells = <1>;ranges = <0 0x01d00000 0x80000>;ve_sram: sram-section@0 {compatible = "allwinner,sun8i-a23-sram-c1","allwinner,sun4i-a10-sram-c1";reg = <0x000000 0x80000>;};};};dma: dma-controller@1c02000 { compatible = "allwinner,sun8i-a23-dma"; reg = <0x01c02000 0x1000>;
@@ -133,6 +161,60 @@ #dma-cells = <1>; };
nfc: nand-controller@1c03000 {compatible = "allwinner,sun8i-a23-nand-controller";reg = <0x01c03000 0x1000>;interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;clock-names = "ahb", "mod";resets = <&ccu RST_BUS_NAND>;reset-names = "ahb";dmas = <&dma 5>;dma-names = "rxtx";pinctrl-names = "default";pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;status = "disabled";#address-cells = <1>;#size-cells = <0>;};tcon0: lcd-controller@1c0c000 {/* compatible gets set in SoC specific dtsi file */reg = <0x01c0c000 0x1000>;interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;dmas = <&dma 12>;clocks = <&ccu CLK_BUS_LCD>,<&ccu CLK_LCD_CH0>,<&ccu 13>;clock-names = "ahb","tcon-ch0","lvds-alt";clock-output-names = "tcon-pixel-clock";#clock-cells = <0>;resets = <&ccu RST_BUS_LCD>,<&ccu RST_BUS_LVDS>;reset-names = "lcd","lvds";status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;tcon0_in: port@0 {reg = <0>;tcon0_in_drc0: endpoint {remote-endpoint = <&drc0_out_tcon0>;};};tcon0_out: port@1 {reg = <1>;};};};- mmc0: mmc@1c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>;
@@ -147,6 +229,8 @@ resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>;@@ -190,21 +274,6 @@ #size-cells = <0>; };
nfc: nand@1c03000 {compatible = "allwinner,sun4i-a10-nand";reg = <0x01c03000 0x1000>;interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;clock-names = "ahb", "mod";resets = <&ccu RST_BUS_NAND>;reset-names = "ahb";pinctrl-names = "default";pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>;status = "disabled";#address-cells = <1>;#size-cells = <0>;};- usb_otg: usb@1c19000 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c19000 0x0400>;
@@ -215,6 +284,7 @@ phys = <&usbphy 0>; phy-names = "usb"; extcon = <&usbphy 0>;
dr_mode = "otg"; status = "disabled";@@ -276,22 +346,30 @@ #interrupt-cells = <3>; #gpio-cells = <3>;
uart0_pins_a: uart0@0 {pins = "PF2", "PF4";function = "uart0";
i2c0_pins: i2c0-pins {pins = "PH2", "PH3";function = "i2c0"; };
uart1_pins_a: uart1@0 {pins = "PG6", "PG7";function = "uart1";
i2c1_pins: i2c1-pins {pins = "PH4", "PH5";function = "i2c1"; };
uart1_pins_cts_rts_a: uart1-cts-rts@0 {pins = "PG8", "PG9";function = "uart1";
i2c2_pins: i2c2-pins {pins = "PE12", "PE13";function = "i2c2"; };
mmc0_pins_a: mmc0@0 {
lcd_rgb666_pins: lcd-rgb666-pins {pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7","PD10", "PD11", "PD12", "PD13", "PD14", "PD15","PD18", "PD19", "PD20", "PD21", "PD22", "PD23","PD24", "PD25", "PD26", "PD27";function = "lcd0";};mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0";@@ -299,7 +377,7 @@ bias-pull-up; };
mmc1_pins_a: mmc1@0 {
mmc1_pg_pins: mmc1-pg-pins { pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "mmc1";@@ -307,7 +385,7 @@ bias-pull-up; };
mmc2_8bit_pins: mmc2_8bit {
mmc2_8bit_pins: mmc2-8bit-pins { pins = "PC5", "PC6", "PC8", "PC9", "PC10", "PC11", "PC12", "PC13", "PC14",@@ -324,61 +402,53 @@ function = "nand0"; };
nand_pins_cs0: nand-pins-cs0 {
nand_cs0_pin: nand-cs0-pin { pins = "PC4"; function = "nand0"; bias-pull-up; };
nand_pins_cs1: nand-pins-cs1 {
nand_cs1_pin: nand-cs1-pin { pins = "PC3"; function = "nand0"; bias-pull-up; };
nand_pins_rb0: nand-pins-rb0 {
nand_rb0_pin: nand-rb0-pin { pins = "PC6"; function = "nand0"; bias-pull-up; };
nand_pins_rb1: nand-pins-rb1 {
nand_rb1_pin: nand-rb1-pin { pins = "PC7"; function = "nand0"; bias-pull-up; };
pwm0_pins: pwm0 {
pwm0_pin: pwm0-pin { pins = "PH0"; function = "pwm0"; };
i2c0_pins_a: i2c0@0 {pins = "PH2", "PH3";function = "i2c0";};i2c1_pins_a: i2c1@0 {pins = "PH4", "PH5";function = "i2c1";
uart0_pf_pins: uart0-pf-pins {pins = "PF2", "PF4";function = "uart0"; };
i2c2_pins_a: i2c2@0 {pins = "PE12", "PE13";function = "i2c2";
uart1_pg_pins: uart1-pg-pins {pins = "PG6", "PG7";function = "uart1"; };
lcd_rgb666_pins: lcd-rgb666@0 {pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7","PD10", "PD11", "PD12", "PD13", "PD14", "PD15","PD18", "PD19", "PD20", "PD21", "PD22", "PD23","PD24", "PD25", "PD26", "PD27";function = "lcd0";
uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {pins = "PG8", "PG9";function = "uart1"; };};
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
compatible = "allwinner,sun8i-a23-timer";
This changes the compatible string, which only started to be supported with Linux v5.4. Any older kernel would not be able to use that timer, but with the arch timer stepping up, we don't lose too much, I guess?
reg = <0x01c20c00 0xa0>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;@@ -389,6 +459,7 @@ compatible = "allwinner,sun6i-a31-wdt"; reg = <0x01c20ca0 0x20>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;};
pwm: pwm@1c21400 {
@@ -477,6 +548,8 @@ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C0>; resets = <&ccu RST_BUS_I2C0>;
pinctrl-names = "default";pinctrl-0 = <&i2c0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>;@@ -488,6 +561,8 @@ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C1>; resets = <&ccu RST_BUS_I2C1>;
pinctrl-names = "default";pinctrl-0 = <&i2c1_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>;@@ -499,6 +574,8 @@ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>;
pinctrl-names = "default";pinctrl-0 = <&i2c2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>;@@ -532,7 +609,7 @@ };
gic: interrupt-controller@1c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, <0x01c82000 0x2000>, <0x01c84000 0x2000>,@@ -542,17 +619,104 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; };
fe0: display-frontend@1e00000 {/* compatible gets set in SoC specific dtsi file */reg = <0x01e00000 0x20000>;interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,<&ccu CLK_DRAM_DE_FE>;clock-names = "ahb", "mod","ram";resets = <&ccu RST_BUS_DE_FE>;ports {#address-cells = <1>;#size-cells = <0>;fe0_out: port@1 {reg = <1>;fe0_out_be0: endpoint {remote-endpoint = <&be0_in_fe0>;};};};};be0: display-backend@1e60000 {/* compatible gets set in SoC specific dtsi file */reg = <0x01e60000 0x10000>;interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,<&ccu CLK_DRAM_DE_BE>;clock-names = "ahb", "mod","ram";resets = <&ccu RST_BUS_DE_BE>;ports {#address-cells = <1>;#size-cells = <0>;be0_in: port@0 {reg = <0>;be0_in_fe0: endpoint {remote-endpoint = <&fe0_out_be0>;};};be0_out: port@1 {reg = <1>;be0_out_drc0: endpoint {remote-endpoint = <&drc0_in_be0>;};};};};drc0: drc@1e70000 {/* compatible gets set in SoC specific dtsi file */reg = <0x01e70000 0x10000>;interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,<&ccu CLK_DRAM_DRC>;clock-names = "ahb", "mod", "ram";resets = <&ccu RST_BUS_DRC>;ports {#address-cells = <1>;#size-cells = <0>;drc0_in: port@0 {reg = <0>;drc0_in_be0: endpoint {remote-endpoint = <&be0_out_drc0>;};};drc0_out: port@1 {reg = <1>;drc0_out_tcon0: endpoint {remote-endpoint = <&tcon0_in_drc0>;};};};};- rtc: rtc@1f00000 {
compatible = "allwinner,sun6i-a31-rtc";reg = <0x01f00000 0x54>;
compatible = "allwinner,sun8i-a23-rtc";
This changes the compatible string, requiring a Linux v5.0 kernel or later to work. While we can probably get over the loss of the actual real-time clock, it is also a clock provider, and the provided clock is used by the CCU and pinctrl drivers.
reg = <0x01f00000 0x400>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clock-output-names = "osc32k";
clock-output-names = "osc32k", "osc32k-out"; clocks = <&ext_osc32k>; #clock-cells = <1>;
nmi_intc: interrupt-controller@1f00c00 {
r_intc: interrupt-controller@1f00c00 { compatible = "allwinner,sun6i-a31-r-intc"; interrupt-controller; #interrupt-cells = <2>;@@ -624,6 +788,20 @@ status = "disabled"; };
r_i2c: i2c@1f02400 {compatible = "allwinner,sun8i-a23-i2c","allwinner,sun6i-a31-i2c";reg = <0x01f02400 0x400>;interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;pinctrl-names = "default";pinctrl-0 = <&r_i2c_pins>;clocks = <&apb0_gates 6>;resets = <&apb0_rst 6>;status = "disabled";#address-cells = <1>;#size-cells = <0>;};- r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-a23-r-pinctrl"; reg = <0x01f02c00 0x400>;
@@ -634,18 +812,22 @@ gpio-controller; interrupt-controller; #interrupt-cells = <3>;
#address-cells = <1>;#size-cells = <0>; #gpio-cells = <3>;r_rsb_pins: r_rsb {
r_i2c_pins: r-i2c-pins {pins = "PL0", "PL1";function = "s_i2c";bias-pull-up;};r_rsb_pins: r-rsb-pins { pins = "PL0", "PL1"; function = "s_rsb"; drive-strength = <20>; bias-pull-up; };
r_uart_pins_a: r_uart@0 {
r_uart_pins_a: r-uart-pins { pins = "PL2", "PL3"; function = "s_uart"; };