On Wed, 2011-02-23 at 11:35 -0500, Kyle Moffett wrote:
The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit integer divide operations to convert between nanoseconds and DDR clock cycles given arbitrary DDR clock frequencies.
Since all of the inputs to this are 32-bit (nanoseconds, clock cycles, and DDR frequencies), we can easily restructure the computation to use the "do_div()" function to perform 64-bit/32-bit divide operations.
This decreases compute time rather significantly for each conversion and avoids bringing in a very complicated function from libgcc.
It should be noted that nothing else in U-Boot or the Linux kernel seems to require a full 64-bit divide on any 32-bit PowerPC.
Build-and-boot-tested on the HWW-1U-1A board using DDR2 SPD detection.
Signed-off-by: Kyle Moffett Kyle.D.Moffett@boeing.com Cc: Andy Fleming afleming@gmail.com Cc: Kumar Gala kumar.gala@freescale.com Cc: Wolfgang Denk wd@denx.de Cc: Kim Phillips kim.phillips@freescale.com
Ok, so this patch touches a rather sensitive part of the fsl_ddr logic.
I spent a fair amount of time trying to verify that the resulting math is exactly the same as it was before, but the consequences of a mistake are insideous timing problems. Additional in-depth review would be much appreciated.
What's the gain of the changes? A smaller footprint? Going forward from 32- to 64-bit, are we going to change it back?
York