The SSP2 clock is at bit 6 in the register, so the value is 0x40 unlike the current 0x70 which enables the clock of UART2, SSP1 and SSP2.
Signed-off-by: Quentin Schulz quentin.schulz@bootlin.com ---
added in v2
@Stefan: I think you'd want to test the FPGA on x600 again as it's using this constant. Having worked on a system close to the x600, I'm guessing that it'll work as fine as on my platform with this patch but better be sure than sorry.
arch/arm/include/asm/arch-spear/spr_misc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h index 01b4b2b..0171119 100644 --- a/arch/arm/include/asm/arch-spear/spr_misc.h +++ b/arch/arm/include/asm/arch-spear/spr_misc.h @@ -151,7 +151,7 @@ struct misc_regs { #define MISC_GPT2ENB 0x00000800 #define MISC_FSMCENB 0x00000200 #define MISC_I2CENB 0x00000080 -#define MISC_SSP2ENB 0x00000070 +#define MISC_SSP2ENB 0x00000040 #define MISC_SSP1ENB 0x00000020 #define MISC_UART0ENB 0x00000008