Hi Stephen,
On Tue, 26 Feb 2013 15:28:28 -0700, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Tegra20 has a Cortex A9 r1p1, and Tegra30 has a Cortex A9 r2p9. As such, some CPU errata exist, and must be worked around.
These must be worked around in the bootloader, since in general, the kernel (especially a multi-platform kernel) needs to support being launched in non-secure mode (normal world), and hence may not be able to write to the CP15 register to enable these workarounds.
Signed-off-by: Stephen Warren swarren@nvidia.com
include/configs/tegra20-common.h | 6 ++++++ include/configs/tegra30-common.h | 6 ++++++ 2 files changed, 12 insertions(+)
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 33e5f52..186e023 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -26,6 +26,12 @@ #include "tegra-common.h"
/*
- Errata configuration
- */
+#define CONFIG_ARM_ERRATA_742230 +#define CONFIG_ARM_ERRATA_751472
+/*
- NS16550 Configuration
*/ #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 04517e1..f6c07c6 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -26,6 +26,12 @@ #include "tegra-common.h"
/*
- Errata configuration
- */
+#define CONFIG_ARM_ERRATA_743622 +#define CONFIG_ARM_ERRATA_751472
+/*
- NS16550 Configuration
*/ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
Applied to u-boot-arm/master, thanks!
Amicalement,