Add functions for use with mx6 soc void otg_enable(void); void reset_usb_phy1(void);
Signed-off-by: Troy Kisky troy.kisky@boundarydevices.com --- arch/arm/cpu/armv7/mx6/soc.c | 47 +++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/crm_regs.h | 3 ++ arch/arm/include/asm/arch-mx6/imx-regs.h | 17 +++++++++++ arch/arm/include/asm/arch-mx6/sys_proto.h | 4 +++ 4 files changed, 71 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 32572ee..37e8c7f 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -12,11 +12,58 @@ #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> #include <asm/arch/sys_proto.h> #include <asm/imx-common/boot_mode.h> #include <asm/imx-common/dma.h> #include <stdbool.h>
+#ifdef CONFIG_MV_UDC +static void enable_usb_phy1_clk(unsigned char enable) +{ + struct usbphy *phy = (struct usbphy *)USB_PHY0_BASE_ADDR; + + writel(BM_USBPHY_CTRL_CLKGATE, + enable ? &phy->ctrl.clr : &phy->ctrl.set); +} + +void reset_usb_phy1(void) +{ + struct usbphy *phy = (struct usbphy *)USB_PHY0_BASE_ADDR; + + /* Reset USBPHY module */ + writel(BM_USBPHY_CTRL_SFTRST, &phy->ctrl.set); + udelay(10); + + /* Remove CLKGATE and SFTRST */ + writel(BM_USBPHY_CTRL_CLKGATE | BM_USBPHY_CTRL_SFTRST, &phy->ctrl.clr); + udelay(10); + + /* Power up the PHY */ + writel(0, &phy->pwd.val); +} + +static void set_usb_phy1_clk(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + + writel(BM_ANADIG_USB1_CHRG_DETECT_EN_B + | BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B, + &anatop->usb1_chrg_detect_set); + + /* make sure pll is enable here */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS, + &anatop->usb1_pll_480_ctrl_set); +} + +void otg_enable(void) +{ + set_usb_phy1_clk(); + enable_usboh3_clk(1); + enable_usb_phy1_clk(1); +} +#endif + struct scu_regs { u32 ctrl; u32 config; diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 74aefe6..364d9a4 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -647,6 +647,9 @@ struct mxc_ccm_reg { #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
+#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000 +#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000 + #define BM_ANADIG_PLL_528_LOCK 0x80000000 #define BP_ANADIG_PLL_528_RSVD1 19 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5d6bccb..3eed4d8 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -419,6 +419,23 @@ struct cspi_regs { ECSPI5_BASE_ADDR #endif
+struct set_clr_tog { + u32 val; + u32 set; + u32 clr; + u32 tog; +}; + +struct usbphy { + struct set_clr_tog pwd; + struct set_clr_tog tx; + struct set_clr_tog rx; + struct set_clr_tog ctrl; +}; + +#define BM_USBPHY_CTRL_CLKGATE 0x40000000 +#define BM_USBPHY_CTRL_SFTRST 0x80000000 + struct ocotp_regs { u32 ctrl; u32 ctrl_set; diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index bfdfd29..4413c3f 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -40,4 +40,8 @@ int mxs_wait_mask_set(struct mxs_register_32 *reg, int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned int timeout); + +void otg_enable(void); +void reset_usb_phy1(void); + #endif