
18 May
2018
18 May
'18
10:11 a.m.
On 05/18/2018 04:05 PM, Ley Foon Tan wrote:
Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch conditional build in order this file can by shared across other SOCFPGAs.
Signed-off-by: Chin Liang See chin.liang.see@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
Applied 01..05, thanks
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Best regards,
Marek Vasut