On Mon, 11 Jan 2021 21:11:38 +0100 Jernej Skrabec jernej.skrabec@siol.net wrote:
I2C support, especially R_I2C port, will be needed in future. Upcoming support for H616 will need R_I2C to adjust DRAM voltage.
Reviewed-by: Samuel Holland samuel@sholland.org Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net
Reviewed-by: Andre Przywara andre.przywara@arm.com
Thanks! Andre
.../include/asm/arch-sunxi/clock_sun50i_h6.h | 1 + arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/clock_sun50i_h6.c | 29 +++++++++++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index 426069fc69a4..e83e84ab6cab 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -297,6 +297,7 @@ struct sunxi_ccm_reg {
/* Module gate/reset shift*/ #define RESET_SHIFT (16) +#define GATE_SHIFT (0)
/* DRAM clock bit field */ #define DRAM_MOD_RESET BIT(30) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index bd82c0ef3ee4..b23ed695cd1c 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -730,7 +730,7 @@ config I2C3_ENABLE See I2C0_ENABLE help text. endif
-if SUNXI_GEN_SUN6I +if SUNXI_GEN_SUN6I || SUN50I_GEN_H6 config R_I2C_ENABLE bool "Enable the PRCM I2C/TWI controller" # This is used for the pmic on H3 diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index ba8a26eb0d36..6bd466915c11 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -2,6 +2,7 @@ #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/clock.h> +#include <asm/arch/prcm.h>
#ifdef CONFIG_SPL_BUILD void clock_init_safe(void) @@ -92,3 +93,31 @@ unsigned int clock_get_pll6(void) /* The register defines PLL6-4X, not plain PLL6 */ return 24000000 / 4 * n / div1 / div2; }
+int clock_twi_onoff(int port, int state) +{
- struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;- struct sunxi_prcm_reg *const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;- u32 value, *ptr;
- int shift;
- value = BIT(GATE_SHIFT) | BIT (RESET_SHIFT);
- if (port == 5) {
shift = 0;ptr = &prcm->twi_gate_reset;- } else {
shift = port;ptr = &ccm->twi_gate_reset;- }
- /* set the apb clock gate and reset for twi */
- if (state)
setbits_le32(ptr, value << shift);- else
clrbits_le32(ptr, value << shift);- return 0;
+}