
On 2022/9/22 20:12, Quentin Schulz wrote:
From: Quentin Schulz quentin.schulz@theobroma-systems.com
Sync the px30 dtsi from linux-next tree, commit 483fed3b5dc8c ("Add linux-next specific files for 20220921").
Cc: Quentin Schulz foss+uboot@0leil.net Signed-off-by: Quentin Schulz quentin.schulz@theobroma-systems.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/px30.dtsi | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi index 00f50b05d5..bfa3580429 100644 --- a/arch/arm/dts/px30.dtsi +++ b/arch/arm/dts/px30.dtsi @@ -365,6 +365,28 @@ status = "disabled"; };
- i2s0_8ch: i2s@ff060000 {
compatible = "rockchip,px30-i2s-tdm";
reg = <0x0 0xff060000 0x0 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
dmas = <&dmac 16>, <&dmac 17>;
dma-names = "tx", "rx";
rockchip,grf = <&grf>;
resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
reset-names = "tx-m", "rx-m";
pinctrl-names = "default";
pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
&i2s0_8ch_lrcktx &i2s0_8ch_lrckrx
&i2s0_8ch_sdo0 &i2s0_8ch_sdi0
&i2s0_8ch_sdo1 &i2s0_8ch_sdi1
&i2s0_8ch_sdo2 &i2s0_8ch_sdi2
&i2s0_8ch_sdo3 &i2s0_8ch_sdi3>;
#sound-dai-cells = <0>;
status = "disabled";
- };
- i2s1_2ch: i2s@ff070000 { compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff070000 0x0 0x1000>;
@@ -528,7 +550,7 @@ i2c0: i2c@ff180000 { compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xff180000 0x0 0x1000>;
clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
clock-names = "i2c", "pclk"; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default";clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
@@ -711,7 +733,7 @@ clock-names = "pclk", "timer"; };
- dmac: dmac@ff240000 {
- dmac: dma-controller@ff240000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff240000 0x0 0x4000>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
@@ -1072,7 +1094,7 @@ };
dsi: dsi@ff450000 {
compatible = "rockchip,px30-mipi-dsi";
reg = <0x0 0xff450000 0x0 0x10000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_MIPI_DSI>;compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi";