Wolfgang Denk wrote:
In message 40280BAF.9090506@iti.fi you wrote:
I have bdi2000, lite5200 and my own board ( itipower5200 ). I noticed that when i boot either board up. I can't read access flash with bdi2000 untill i have executed some amount of initial code that exists in lite5200 but of cource i can do this with my board because there is no code in flash yet.
Which BDI2000 configuration file are you using?
I have been using various versions. Now i use mpc5200.cfg.flash from ftp.denx.de
What's the exactl difference between our config file and yours?
only modifications host ip address and u-boot load path.
Argh... Did you try using the config file from our FTP server?
Yes i used. The following log is with bdi2000 with working lite5200 board and mpc5200.cfg.flash config file. I get the flash visible only after using TI command several times in bdi2000 commad level.
Kate
BDI>reset halt - TARGET: processing user reset request - BDI asserts HRESET - Reset JTAG controller passed - Bypass check: 0x55 => 0xAA - Bypass check: 0x55 => 0xAA - JTAG exists check passed - Target PVR is 0x80822011 - Target SVR is 0x80110012 - COP status is 0x01 - Check running state passed - BDI scans COP freeze command - BDI removes HRESET - COP status is 0x05 - Check stopped state passed - Check LSRL length passed - BDI sets breakpoint at 0xFFF00100 - BDI resumes program execution - Waiting for target stop passed - TARGET: Target PVR is 0x80822011 - TARGET: resetting target passed - TARGET: processing target startup .... - Target MBAR is 0x80000000 - Target XLBA is 0x80000006 - TARGET: processing target startup passed BDI>md 0xfff00100 fff00100 : 00000000 00000000 00000000 00000000 ................
BDI>md 0xf0000000 f0000000 : 0000f000 0000ff80 0000ffff 0000ffff ................ f0000010 : 0000ffff 0000ffff 0000ffff 0000ffff ................ f0000020 : 0000ffff 0000ffff 0000ffff 0000ffff ................ f0000030 : 0000ffff 00000000 00000000 0000ffff ................ f0000040 : 0000ffff 0000ffff 0000ffff 0000fff0 ................ f0000050 : 0000fff7 00010001 0000ffff 0000ffff ................ f0000060 : 0000ffff 0000ffff 00000000 00000000 ................
BDI>md 0xf0000300 f0000300 : 000f7800 00004000 00004000 00004000 ..x...@...@...@. f0000310 : 00004000 00004000 00000000 00000000 ..@...@......... f0000320 : 00004000 00004000 00000000 33333333 ..@...@.....3333 f0000330 : 00000000 00000000 00000000 00000000 ................ f0000340 : 00000000 00000000 00000000 00000000 ................ f0000350 : 00000000 00000000 00000000 00000000 ................ f0000360 : 00000000 00000000 00000000 00000000 ................ f0000370 : 00000000 00000000 00000000 00000000 ................
BDI>ti - Target MBAR is 0xF0000000 - Target XLBA is 0x80000006 BDI> Target CPU : MPC8280/MGT5200 (Zeppo) Target state : debug mode Debug entry cause : trace Current PC : 0xfff00104
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BDI>ti - Target MBAR is 0xF0000000 - Target XLBA is 0x80000006 BDI> Target CPU : MPC8280/MGT5200 (Zeppo) Target state : debug mode Debug entry cause : trace Current PC : 0xfff001d8 Current CR : 0x80000000 Current MSR : 0x00001002 Current LR : 0xfff00118 BDI>md 0xfff00100 fff00100 : 00000000 00000000 00000000 00000000 ................ fff00110 : 00000000 00000000 00000000 00000000 ................
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BDI>ti - Target MBAR is 0xF0000000 - Target XLBA is 0x80000006 BDI> Target CPU : MPC8280/MGT5200 (Zeppo) Target state : debug mode Debug entry cause : trace Current PC : 0xfff02000 Current CR : 0x80000000 Current MSR : 0x00001002 Current LR : 0xfff001f0 BDI>md 0xfff00100 fff00100 : 00000000 00000000 00000000 00000000 ................
- Target MBAR is 0xF0000000 - Target XLBA is 0x80000006 BDI> Target CPU : MPC8280/MGT5200 (Zeppo) Target state : debug mode Debug entry cause : COP halt Current PC : 0xfff0d61c Current CR : 0x40000000 Current MSR : 0x00001002 Current LR : 0xfff0d544 # Step timeout detected BDI>md 0xfff00100 fff00100 : 7ff043a6 7fe802a6 7ff143a6 7c774aa6 ..C.......C.|wJ. fff00110 : 7c631b79 408200bd 3c608000 60630000 |c.y@...<`..`c..