[U-Boot] [PATCH v5 11/26] clk: sunxi: Implement UART clocks

Implement UART clocks for all Allwinner SoC clock drivers via ccu clock gate table.

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/clk_a10.c | 9 +++++++++ drivers/clk/sunxi/clk_a10s.c | 5 +++++ drivers/clk/sunxi/clk_a23.c | 6 ++++++ drivers/clk/sunxi/clk_a31.c | 7 +++++++ drivers/clk/sunxi/clk_a64.c | 6 ++++++ drivers/clk/sunxi/clk_a83t.c | 6 ++++++ drivers/clk/sunxi/clk_h3.c | 5 +++++ drivers/clk/sunxi/clk_r40.c | 9 +++++++++ drivers/clk/sunxi/clk_v3s.c | 4 ++++ 9 files changed, 57 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index 59d9d90a19..1b074e3872 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -19,6 +19,15 @@ static struct ccu_clk_gate a10_gates[] = { [CLK_AHB_EHCI1] = GATE(0x060, BIT(3)), [CLK_AHB_OHCI1] = GATE(0x060, BIT(4)),

+ [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), + [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), + [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), + [CLK_APB1_UART3] = GATE(0x06c, BIT(19)), + [CLK_APB1_UART4] = GATE(0x06c, BIT(20)), + [CLK_APB1_UART5] = GATE(0x06c, BIT(21)), + [CLK_APB1_UART6] = GATE(0x06c, BIT(22)), + [CLK_APB1_UART7] = GATE(0x06c, BIT(23)), + [CLK_USB_OHCI0] = GATE(0x0cc, BIT(6)), [CLK_USB_OHCI1] = GATE(0x0cc, BIT(7)), [CLK_USB_PHY] = GATE(0x0cc, BIT(8)), diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index 474f37d607..a50c6e3f7f 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -17,6 +17,11 @@ static struct ccu_clk_gate a10s_gates[] = { [CLK_AHB_EHCI] = GATE(0x060, BIT(1)), [CLK_AHB_OHCI] = GATE(0x060, BIT(2)),

+ [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), + [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), + [CLK_APB1_UART2] = GATE(0x06c, BIT(18)), + [CLK_APB1_UART3] = GATE(0x06c, BIT(19)), + [CLK_USB_OHCI] = GATE(0x0cc, BIT(6)), [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 0fc8a5821c..63004b881d 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -17,6 +17,12 @@ static struct ccu_clk_gate a23_gates[] = { [CLK_BUS_EHCI] = GATE(0x060, BIT(26)), [CLK_BUS_OHCI] = GATE(0x060, BIT(29)),

+ [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), + [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), + [CLK_BUS_UART4] = GATE(0x06c, BIT(20)), + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)), diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index 03dd9ae913..c01d2a3549 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -20,6 +20,13 @@ static struct ccu_clk_gate a31_gates[] = { [CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)), [CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),

+ [CLK_APB2_UART0] = GATE(0x06c, BIT(16)), + [CLK_APB2_UART1] = GATE(0x06c, BIT(17)), + [CLK_APB2_UART2] = GATE(0x06c, BIT(18)), + [CLK_APB2_UART3] = GATE(0x06c, BIT(19)), + [CLK_APB2_UART4] = GATE(0x06c, BIT(20)), + [CLK_APB2_UART5] = GATE(0x06c, BIT(21)), + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)), diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 28bda1f497..b427e3adda 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -19,6 +19,12 @@ static const struct ccu_clk_gate a64_gates[] = { [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)), [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),

+ [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), + [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), + [CLK_BUS_UART4] = GATE(0x06c, BIT(20)), + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)), diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index 45faef2f11..fbffa3bf5f 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -18,6 +18,12 @@ static struct ccu_clk_gate a83t_gates[] = { [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),

+ [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), + [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), + [CLK_BUS_UART4] = GATE(0x06c, BIT(20)), + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)), diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index 283fc31b01..f706e77dee 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -23,6 +23,11 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)), [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),

+ [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), + [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)), diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index 2a6000f4dc..3405b39c46 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -21,6 +21,15 @@ static struct ccu_clk_gate r40_gates[] = { [CLK_BUS_OHCI1] = GATE(0x060, BIT(30)), [CLK_BUS_OHCI2] = GATE(0x060, BIT(31)),

+ [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), + [CLK_BUS_UART3] = GATE(0x06c, BIT(19)), + [CLK_BUS_UART4] = GATE(0x06c, BIT(20)), + [CLK_BUS_UART5] = GATE(0x06c, BIT(21)), + [CLK_BUS_UART6] = GATE(0x06c, BIT(22)), + [CLK_BUS_UART7] = GATE(0x06c, BIT(23)), + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)), diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 0eeea84c1a..a662bc3e93 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -15,6 +15,10 @@ static struct ccu_clk_gate v3s_gates[] = { [CLK_BUS_OTG] = GATE(0x060, BIT(24)),

+ [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), + [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), + [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), };