On Tuesday, August 18, 2015 at 10:27:29 PM, Dinh Nguyen wrote:
On 8/10/15 6:00 PM, Marek Vasut wrote:
Based on observation, this udelay(20) was apparently too high and caused subsequent failure to calibrate DDR when U-Boot was compiled with certain toolchains. Lowering this delay fixed the problem.
Instead of permanently lowering the delay, calculate the correct delay based on the original comment, that is, obtain EOSC1 frequency and use it to calculate the precise delay.
Signed-off-by: Marek Vasut marex@denx.de
arch/arm/mach-socfpga/freeze_controller.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c index 0be643c..2b16795 100644 --- a/arch/arm/mach-socfpga/freeze_controller.c +++ b/arch/arm/mach-socfpga/freeze_controller.c @@ -7,8 +7,8 @@
Acked-by: Dinh Nguyen dinguyen@opensource.altera.com
Applied to u-boot-socfpga/master, thanks!
Best regards, Marek Vasut