Add the compatible entry and corresponding chip data for Exynos7 compatible chips, which covers modern ARM64 based Exynos chips. They have some differences w.r.t. old ARM32 Exynos chips: - CLKSEL register offset is different - 64-bit IDMAC descriptor and 64-bit IDMAC registers are used (implemented in dw_mmc core driver)
In terms of the driver implementation, the CIU clock is obtained via CCF framework (as opposed to ad-hoc clock driver implementation for ARM32 chips).
Signed-off-by: Sam Protsenko semen.protsenko@linaro.org --- Changes in v3: - (none)
Changes in v2: - (none)
arch/arm/mach-exynos/include/mach/dwmmc.h | 1 + drivers/mmc/exynos_dw_mmc.c | 8 ++++++++ 2 files changed, 9 insertions(+)
diff --git a/arch/arm/mach-exynos/include/mach/dwmmc.h b/arch/arm/mach-exynos/include/mach/dwmmc.h index 811e9a04c6e3..7cb71be0d9fd 100644 --- a/arch/arm/mach-exynos/include/mach/dwmmc.h +++ b/arch/arm/mach-exynos/include/mach/dwmmc.h @@ -8,6 +8,7 @@ #define __ASM_ARM_ARCH_DWMMC_H
#define DWMCI_CLKSEL 0x09C +#define DWMCI_CLKSEL64 0x0a8 #define DWMCI_SET_SAMPLE_CLK(x) (x) #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24) diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index ee3ae9f5e650..29241edf7915 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -385,6 +385,11 @@ static const struct exynos_dwmmc_variant exynos5_drv_data = { #endif };
+static const struct exynos_dwmmc_variant exynos7_smu_drv_data = { + .clksel = DWMCI_CLKSEL64, + .quirks = DWMCI_QUIRK_DISABLE_SMU, +}; + static const struct udevice_id exynos_dwmmc_ids[] = { { .compatible = "samsung,exynos4412-dw-mshc", @@ -392,6 +397,9 @@ static const struct udevice_id exynos_dwmmc_ids[] = { }, { .compatible = "samsung,exynos-dwmmc", .data = (ulong)&exynos5_drv_data, + }, { + .compatible = "samsung,exynos7-dw-mshc-smu", + .data = (ulong)&exynos7_smu_drv_data, }, { } };