Re: [U-Boot] [PATCH 10/11] tegra20: remove old pinmux setup

On 01/25/2013 02:19 PM, Lucas Stach wrote:

Am Freitag, den 25.01.2013, 14:12 -0800 schrieb Stephen Warren:

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On 01/24/2013 08:48 AM, Lucas Stach wrote:

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All boards are converted to the new tablebased pinmux setup. Get rid of the old method.

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diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c

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@@ -145,7 +121,6 @@ static void setup_uarts(int uart_ids) if (uart_ids & (1 << i)) { enum periph_id id = id_for_uart[i];

• 	funcmux_select(id, uart_configs[i]);
  clock_ll_start_uart(id);
  

  } }

Doesn't the debug UART get set up very early, in the SPL, before any table-based pinmux could be activated?

If so, I think we need to leave this one funcmux API call in place, so that the debug UART always works nice and early.

If not, how much does this series increase the binary of the SPL?

Ah right, I forgot about SPL debug. If we go for FDT based pinmux, we have to init UART in some explicit way, as DT and SPL don't mix.

But even then I would like to get rid of the funcmux style and rather let the boards provide a minimal UART pinmux init table, as funcmux doesn't map too well onto the plethora of config options Tegra30 provides for the pinmux.

Yes, that's perhaps true.

For reference, I recently worked out all the possible locations of each logical signal (well, only RX/TX/RTS/CTS for Tegra30) for each UART. I put the table below for reference in case it's interesting.

Tegra20:

(sets of pingroups that create a complete UART)

• • UART A:

• • 0: unspecified
    

• • 1: irrx, irtx
    

• • 2: gpu
    

• • 3: sdb, sdd
    

• • 4: sdio1
    

• • 5: uaa
    

• • 6: irrx, irtx, uad
    

• • 7: irrx, irtx, uad, uab
    

• • 8: sdb, sdd, uad
    

• • 9: sdb, sdd, uad, uab
    

• • 10: uaa, uab
    

• • UART B:

• • 0: unspecified
    

• • 1: uad
    

• • 2: uad, irrx, irtx
    

• • UART C:

• • 0: unspecified
    

• • 1: uca
    

• • 2: uca, ucb
    

• • UART D:

• • 0: unspecified
    

• • 1: gmc
    

• • 2: uda
    

• • UART E:

• • 0: unspecified
    

• • 1: gma
    

• • 2: sdio1
    

Tegra30:

(possible locations for each signal on each UART)

• • UART CTS pin
• • UART A:

• • 0: unspecified
    

• • 1: uart2_rxd
    

• • 2: ulpi_data2
    

• • 3: gpio_pu2
    

• • UART B:

• • 0: unspecified
    

• • 1: uart2_cts_n
    

• • UART C:

• • 0: unspecified
    

• • 1: uart3_cts_n
    

• • UART D:

• • 0: unspecified
    

• • 1: gmi_a18
    

• • 2: ulpi_nxt
    

• • UART E:

• • 0: unspecified
    

• • 1: sdmmc1_dat1
    

• • 2: sdmmc4_dat2
    

• • UART RTS pin
• • UART A:

• • 0: unspecified
    

• • 1: uart2_txd
    

• • 2: ulpi_data3
    

• • 3: gpio_pu3
    

• • UART B:

• • 0: unspecified
    

• • 1: uart2_rts_n
    

• • UART C:

• • 0: unspecified
    

• • 1: uart3_rts_n
    

• • UART D:

• • 0: unspecified
    

• • 1: gmi_a19
    

• • 2: ulpi_stp
    

• • UART E:

• • 0: unspecified
    

• • 1: sdmmc1_dat0
    

• • 2: sdmmc4_dat3
    

• • UART TXD pin
• • UART A:

• • 0: unspecified
    

• • 1: sdmmc3_clk
    

• • 2: uart2_rts_n
    

• • 3: ulpi_data0
    

• • 4: gpio_pu0
    

• • UART B:

• • 0: unspecified
    

• • 1: uart2_txd
    

• • UART C:

• • 0: unspecified
    

• • 1: uart3_txd
    

• • UART D:

• • 0: unspecified
    

• • 1: gmi_a16
    

• • 2: ulpi_clk
    

• • UART E:

• • 0: unspecified
    

• • 1: sdmmc1_dat3
    

• • 2: sdmmc4_dat0
    

• • UART RXD pin
• • UART A:

• • 0: unspecified
    

• • 1: sdmmc3_cmd
    

• • 2: uart2_cts_n
    

• • 3: ulpi_data1
    

• • 4: gpio_pu1
    

• • UART B:

• • 0: unspecified
    

• • 1: uart2_rxd
    

• • UART C:

• • 0: unspecified
    

• • 1: uart3_rxd
    

• • UART D:

• • 0: unspecified
    

• • 1: gmi_a17
    

• • 2: ulpi_dir
    

• • UART E:

• • 0: unspecified
    

• • 1: sdmmc1_dat2
    

• • 2: sdmmc4_dat1