There is nothing special about the ivybridge pci driver now, so just use the generic one.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: - Drop the special compatible string in chromebook_link.dts
arch/x86/cpu/ivybridge/Makefile | 1 - arch/x86/cpu/ivybridge/pci.c | 46 ---------------------------------------- arch/x86/dts/chromebook_link.dts | 2 +- 3 files changed, 1 insertion(+), 48 deletions(-) delete mode 100644 arch/x86/cpu/ivybridge/pci.c
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index bdbd3fa..259a5df 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -15,7 +15,6 @@ obj-y += model_206ax.o obj-y += microcode_intel.o obj-y += northbridge.o obj-y += pch.o -obj-y += pci.o obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c deleted file mode 100644 index 5195002..0000000 --- a/arch/x86/cpu/ivybridge/pci.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008,2009 - * Graeme Russ, graeme.russ@gmail.com - * - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <pci.h> -#include <asm/pci.h> -#include <asm/post.h> -#include <asm/arch/bd82x6x.h> -#include <asm/arch/pch.h> - -static int pci_ivybridge_probe(struct udevice *bus) -{ - if (!(gd->flags & GD_FLG_RELOC)) - return 0; - post_code(0x50); - post_code(0x51); - - return 0; -} - -static const struct dm_pci_ops pci_ivybridge_ops = { - .read_config = pci_x86_read_config, - .write_config = pci_x86_write_config, -}; - -static const struct udevice_id pci_ivybridge_ids[] = { - { .compatible = "intel,pci-ivybridge" }, - { } -}; - -U_BOOT_DRIVER(pci_ivybridge_drv) = { - .name = "pci_ivybridge", - .id = UCLASS_PCI, - .of_match = pci_ivybridge_ids, - .ops = &pci_ivybridge_ops, - .probe = pci_ivybridge_probe, -}; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 022b04c..18305a3 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -193,7 +193,7 @@ };
pci { - compatible = "intel,pci-ivybridge", "pci-x86"; + compatible = "pci-x86"; #address-cells = <3>; #size-cells = <2>; u-boot,dm-pre-reloc;