From: Martha Marx mmarx@silicontkx.com
The following configurations are now supported:
ads5121_config rev 4.1 boards with Elpida memory
ads5121_rev4m_config rev 4 boards with Micron memory
ads5121_rev3_config rev3 boards which also have Micron memory but have the older rev silicon
Signed-off-by: Martha Marx mmarx@silicontkx.com --- Makefile | 8 ++++++ board/ads5121/ads5121.c | 61 ++++++++++++++++++++++++++++++-------------- include/configs/ads5121.h | 28 ++++++++++++++------ 3 files changed, 68 insertions(+), 29 deletions(-)
diff --git a/Makefile b/Makefile index ee82c5d..b77532c 100644 --- a/Makefile +++ b/Makefile @@ -792,11 +792,19 @@ v38b_config: unconfig
ads5121_config \ ads5121_rev2_config \ +ads5121_rev3_config \ +ads5121_rev4m_config \ : unconfig @mkdir -p $(obj)include @if [ "$(findstring rev2,$@)" ] ; then \ echo "#define CONFIG_ADS5121_REV2 1" > $(obj)include/config.h; \ fi + @if [ "$(findstring rev3,$@)" ] ; then \ + echo "#define CONFIG_ADS5121_REV3 1" > $(obj)include/config.h; \ + fi + @if [ "$(findstring rev4m,$@)" ] ; then \ + echo "#define CONFIG_ADS5121_REV4M 1" > $(obj)include/config.h; \ + fi @$(MKCONFIG) -a ads5121 ppc mpc512x ads5121
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 6c40e94..cb607b4 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -182,29 +182,50 @@ long int fixed_sdram (void)
/* Initialize DDR */ for (i = 0; i < 10; i++) - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + + im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; +#if defined(CONFIG_ADS5121_REV2) || \ + defined(CONFIG_ADS5121_REV3) || \ + defined(CONFIG_ADS5121_REV4M) + /* Micron init sequence */ im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL; + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2; + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2; + im->mddrc.ddr_command = CONFIG_SYS_DDR_EM3; + im->mddrc.ddr_command = CONFIG_SYS_DDR_EN_DLL; im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; +#else + /* Elpida init sequence */ + im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2; + im->mddrc.ddr_command = CONFIG_SYS_DDR_EM3; + im->mddrc.ddr_command = CONFIG_SYS_DDR_EN_DLL; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RES_DLL; + im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_ELPIDA_INIT_DEV_OP; + udelay(200); +#endif + im->mddrc.ddr_command = CONFIG_SYS_DDR_OCD_DEFAULT; + im->mddrc.ddr_command = CONFIG_SYS_DDR_OCD_EXIT; + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + for (i = 0; i < 10; i++) + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP;
/* Start MDDRC */ im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN; diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 8fda3f2..2e6ceef 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -135,24 +135,34 @@ #define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 -#else +#elif defined(CONFIG_ADS5121_REV3) || \ + defined(CONFIG_ADS5121_REV4M) #define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 #define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 +#else +#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA802b40 +#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA802b40 +#define CONFIG_SYS_MDDRC_TIME_CFG1 0x690e1189 +#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35410864 #endif #define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 +#define CONFIG_SYS_MDDRC_SYS_CFG_CLK_BIT (1 << 29) +#define CONFIG_SYS_MDDRC_SYS_CFG_CKE_BIT (1 << 30) #define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E #define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EM2 0x01020000 -#define CONFIG_SYS_MICRON_EM3 0x01030000 -#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 +#define CONFIG_SYS_ELPIDA_INIT_DEV_OP 0x01000842 +#define CONFIG_SYS_DDR_NOP 0x01380000 +#define CONFIG_SYS_DDR_PCHG_ALL 0x01100400 +#define CONFIG_SYS_DDR_EM2 0x01020000 +#define CONFIG_SYS_DDR_EM3 0x01030000 +#define CONFIG_SYS_DDR_EN_DLL 0x01010000 +#define CONFIG_SYS_DDR_RES_DLL 0x01000932 +#define CONFIG_SYS_DDR_RFSH 0x01080000 +#define CONFIG_SYS_DDR_OCD_DEFAULT 0x01010780 +#define CONFIG_SYS_DDR_OCD_EXIT 0x01010400
/* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777