On Wed, 02 May 2012 19:45:15 +0100, Luka Perkov uboot@lukaperkov.net wrote:
Hi Jamie,
I know that you have sent newer version of this patch but here is easier for me to comment... I have also put maintainer of NAS325 board in CC.
On Thu, Apr 26, 2012 at 11:23:58AM +0100, Jamie Lentin wrote:
This patch adds support for D-Link DNS-320 ShareCenter NAS.
...
+#ifdef CONFIG_RESET_PHY_R +/* Configure and initialize PHY */ +void reset_phy(void) +{
- u16 reg;
- u16 devadr;
- char *name = "egiga0";
- if (miiphy_set_current_dev(name))
return;- /* command to read PHY dev address */
- if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
printf("Err..(%s) could not read PHY dev address\n", __func__);return;- }
- /*
* Enable RGMII delay on Tx and Rx for CPU port* Ref: sec 4.7.2 of chip datasheet*/- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
- miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
- reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
- miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
- miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
- /* reset the phy */
- miiphy_reset(name, devadr);
- debug("88E1116 Initialized on %s\n", name);
+} +#endif /* CONFIG_RESET_PHY_R */
Are you sure you need this CONFIG_RESET_PHY_R at all? I mean I have the same SoC and I do not need this at all. I think this part is left over from other boards that we do not need anymore. It makes sense to remove this if you do not need it on your board.
Take a look here:
http://git.denx.de/?p=u-boot/u-boot-arm.git;a=blob;f=board/raidsonic/ib62x0/...
I've fiddled for a while and cannot get a working Ethernet connection without this code to enable RGMII delay. Tried cloning configs/ib62x0.h, but no luck. Presumably you have the same PHY chip (88E1116R-NNC1) too?
Agree that it's a copy and pasted chunk of code that shouldn't be there though and at least should find a common home somewhere.
Luka