The JH7110 clock and reset dt-bindings are synchronized with Linux, so update the clock and reset definitions in device tree accordingly.
Signed-off-by: Hal Feng hal.feng@starfivetech.com --- .../dts/jh7110-starfive-visionfive-2.dtsi | 6 ++-- arch/riscv/dts/jh7110-u-boot.dtsi | 2 +- arch/riscv/dts/jh7110.dtsi | 28 +++++++++---------- 3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi index e11babc1cd..2666fd4696 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi @@ -334,9 +334,9 @@ <&syscrg JH7110_SYSCLK_BUS_ROOT>, <&syscrg JH7110_SYSCLK_PERH_ROOT>, <&syscrg JH7110_SYSCLK_QSPI_REF>; - assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>, - <&pllclk JH7110_SYSCLK_PLL2_OUT>, - <&pllclk JH7110_SYSCLK_PLL2_OUT>, + assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; assigned-clock-rates = <0>, <0>, <0>, <0>; }; diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index c09d5c9170..56530cf4c2 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -62,7 +62,7 @@ <&syscrg JH7110_SYSRST_DDR_OSC>, <&syscrg JH7110_SYSRST_DDR_APB>; reset-names = "axi", "osc", "apb"; - clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; clock-names = "pll1_out"; clock-frequency = <2133>; }; diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 2cdc683d49..dbce57c421 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -503,9 +503,9 @@ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, <&tdm_ext>, <&mclk_ext>, - <&pllclk JH7110_SYSCLK_PLL0_OUT>, - <&pllclk JH7110_SYSCLK_PLL1_OUT>, - <&pllclk JH7110_SYSCLK_PLL2_OUT>; + <&pllclk JH7110_PLLCLK_PLL0_OUT>, + <&pllclk JH7110_PLLCLK_PLL1_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", @@ -646,10 +646,10 @@ rng: rng@1600c000 { compatible = "starfive,jh7110-trng"; reg = <0x0 0x1600C000 0x0 0x4000>; - clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>, - <&stgcrg JH7110_STGCLK_SEC_MISCAHB>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, + <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; clock-names = "hclk", "ahb"; - resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; interrupts = <30>; };
@@ -707,12 +707,12 @@ bus-range = <0x0 0xff>; clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, <&stgcrg JH7110_STGCLK_PCIE0_TL>, - <&stgcrg JH7110_STGCLK_PCIE0_AXI>, + <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>, <&stgcrg JH7110_STGCLK_PCIE0_APB>; clock-names = "noc", "tl", "axi", "apb"; - resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>, - <&stgcrg JH7110_STGRST_PCIE0_SLV0>, - <&stgcrg JH7110_STGRST_PCIE0_SLV>, + resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>, + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>, + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>, <&stgcrg JH7110_STGRST_PCIE0_BRG>, <&stgcrg JH7110_STGRST_PCIE0_CORE>, <&stgcrg JH7110_STGRST_PCIE0_APB>; @@ -744,12 +744,12 @@ bus-range = <0x0 0xff>; clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, <&stgcrg JH7110_STGCLK_PCIE1_TL>, - <&stgcrg JH7110_STGCLK_PCIE1_AXI>, + <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>, <&stgcrg JH7110_STGCLK_PCIE1_APB>; clock-names = "noc", "tl", "axi", "apb"; - resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>, - <&stgcrg JH7110_STGRST_PCIE1_SLV0>, - <&stgcrg JH7110_STGRST_PCIE1_SLV>, + resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>, + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>, + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>, <&stgcrg JH7110_STGRST_PCIE1_BRG>, <&stgcrg JH7110_STGRST_PCIE1_CORE>, <&stgcrg JH7110_STGRST_PCIE1_APB>;