11 Nov
2014
11 Nov
'14
9:28 a.m.
Hi John,
On 10/11/2014 00:53, John Tobias wrote:
@@ -29,7 +29,9 @@ #define CONFIG_SPL_TEXT_BASE 0x00908000 #define CONFIG_SPL_MAX_SIZE 0x10000 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7" +#ifndef CONFIG_SPL_STACK #define CONFIG_SPL_STACK 0x0091FFB8 +#endif
Why is this required ?
Other iMX6 chip has different STACK address and the current defined address does not compatibile for the iMX6 SabreSD.
This is exactly what I have not understood. Why is this board so special to require a different value ? SPL will run into the IRAM, whose size and layout is the same for i.MX6Q. Is there a reserved area in the IRAM only for sabreSD and if yes, for which reason ?
Best regards, Stefano Babic
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