Hi Akshay,
On 15 January 2015 at 06:42, Akshay Saraswat akshay.s@samsung.com wrote:
This patch adds workaround for ARM errata 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock."
Signed-off-by: Kimoon Kim kimoon.kim@samsung.com Signed-off-by: Akshay Saraswat akshay.s@samsung.com
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c index 43c957b..7073c5c 100644 --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c @@ -45,6 +45,28 @@ enum {
#ifdef CONFIG_EXYNOS5420 /*
- Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
- stalled for 1024 cycles to verify that its hazard condition still exists.
- */
+void set_l2cache(void) +{
uint32_t val;/* Read MIDR for Primary Part Number*/
Nit: Space before */
mrc_midr(val);val = (val >> 4);val &= 0xf;/* L2ACTLR[7]: Enable hazard detect timeout for A15 */if (val == 0xf) {mrc_l2_aux_ctlr(val);val |= (1 << 7);mcr_l2_aux_ctlr(val);mrc_l2_ctlr(val);}+}
+/*
- Pointer to this function is stored in iRam which is used
- for jump and power down of a specific core.
*/
1.9.1
Reviewed-by: Simon Glass sjg@chromium.org
Tested on snow, pit, pi Tested-by: Simon Glass sjg@chromium.org
Regards, Simon