This patch updates reset controller node for mt7628
Signed-off-by: Weijie Gao weijie.gao@mediatek.com --- arch/mips/dts/mt7628a.dtsi | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-)
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index f07de1b611..0e2b6598ea 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/reset/mt7628-reset.h>
/ { #address-cells = <1>; @@ -16,11 +17,6 @@ }; };
- resetc: reset-controller { - compatible = "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - cpuintc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; @@ -48,6 +44,12 @@ mask = <0x1>; };
+ rstctrl: rstctrl@0x34 { + reg = <0x34 0x4>; + compatible = "mediatek,mtmips-reset"; + #reset-cells = <1>; + }; + pinctrl: pinctrl@60 { compatible = "mediatek,mt7628-pinctrl"; reg = <0x3c 0x2c>, <0x1300 0x100>; @@ -202,7 +204,7 @@ compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt"; reg = <0x100 0x30>;
- resets = <&resetc 8>; + resets = <&rstctrl MT7628_TIMER_RST>; reset-names = "wdt";
interrupt-parent = <&intc>; @@ -216,7 +218,7 @@ interrupt-controller; #interrupt-cells = <1>;
- resets = <&resetc 9>; + resets = <&rstctrl MT7628_INT_RST>; reset-names = "intc";
interrupt-parent = <&cpuintc>; @@ -239,6 +241,9 @@ compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio"; reg = <0x600 0x100>;
+ resets = <&rstctrl MT7628_PIO_RST>; + reset-names = "pio"; + interrupt-parent = <&intc>; interrupts = <6>;
@@ -267,6 +272,10 @@ spi0: spi@b00 { compatible = "ralink,mt7621-spi"; reg = <0xb00 0x40>; + + resets = <&rstctrl MT7628_SPI_RST>; + reset-names = "spi"; + #address-cells = <1>; #size-cells = <0>;
@@ -282,7 +291,7 @@
clock-frequency = <40000000>;
- resets = <&resetc 12>; + resets = <&rstctrl MT7628_UART0_RST>; reset-names = "uart0";
interrupt-parent = <&intc>; @@ -300,7 +309,7 @@
clock-frequency = <40000000>;
- resets = <&resetc 19>; + resets = <&rstctrl MT7628_UART1_RST>; reset-names = "uart1";
interrupt-parent = <&intc>; @@ -318,7 +327,7 @@
clock-frequency = <40000000>;
- resets = <&resetc 20>; + resets = <&rstctrl MT7628_UART2_RST>; reset-names = "uart2";
interrupt-parent = <&intc>; @@ -333,6 +342,9 @@ reg = <0x10100000 0x10000 0x10110000 0x8000>;
+ resets = <&rstctrl MT7628_EPHY_RST>; + reset-names = "ephy"; + syscon = <&sysc>; };
@@ -343,8 +355,8 @@ #phy-cells = <0>;
ralink,sysctl = <&sysc>; - resets = <&resetc 22 &resetc 25>; - reset-names = "host", "device"; + resets = <&rstctrl MT7628_UPHY_RST>; + reset-names = "phy"; };
ehci@101c0000 {