Enable the undefined length INCR burst type and set INCRx. Different platforms may has the different burst size type. In order to get best performance, we need to tune the burst size to one special value, instead of the default value.
Refer to Linux commit (“usb: dwc3: Enable undefined length INCR burst type”)
Signed-off-by: Ran Wang ran.wang_1@nxp.com --- drivers/usb/dwc3/core.c | 95 +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 13 +++++++ 2 files changed, 108 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index f1b970e..52d8242 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -310,6 +310,99 @@ static void dwc3_free_scratch_buffers(struct dwc3 *dwc) kfree(dwc->scratchbuf); }
+#if CONFIG_IS_ENABLED(DM_USB) +/* set global incr burst type configuration registers */ +static void dwc3_set_incr_burst_type(struct dwc3 *dwc) +{ + struct udevice *dev = dwc->dev; + bool incrx_mode; + u32 incrx_size; + u32 *vals; + u32 cfg; + int ntype; + int ret; + int i; + + cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); + + /* + * Handle property "snps,incr-burst-type-adjustment". + * Get the number of value from this property: + * result <= 0, means this property is not supported. + * result = 1, means INCRx burst mode supported. + * result > 1, means undefined length burst mode supported. + */ + ntype = dev_read_size(dev, "snps,incr-burst-type-adjustment") / sizeof(u32); + if (ntype <= 0) + return; + + vals = memalign(CONFIG_SYS_CACHELINE_SIZE, ntype * sizeof(u32)); + if (!vals) { + dev_err(dev, "Error to get memory\n"); + return; + } + + /* Get INCR burst type, and parse it */ + ret = dev_read_u32_array(dev, "snps,incr-burst-type-adjustment", vals, ntype); + if (ret) { + kfree(vals); + dev_err(dev, "Error to get property\n"); + return; + } + + incrx_size = *vals; + + if (ntype > 1) { + /* INCRX (undefined length) burst mode */ + incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; + for (i = 1; i < ntype; i++) { + if (vals[i] > incrx_size) + incrx_size = vals[i]; + } + } else { + /* INCRX burst mode */ + incrx_mode = INCRX_BURST_MODE; + } + + kfree(vals); + + /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ + cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; + if (incrx_mode) + cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; + switch (incrx_size) { + case 256: + cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; + break; + case 128: + cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; + break; + case 64: + cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; + break; + case 32: + cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; + break; + case 16: + cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; + break; + case 8: + cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; + break; + case 4: + cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; + break; + case 1: + break; + default: + dev_err(dev, "Invalid property\n"); + break; + } + + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); +} +#endif + /* * dwc3_frame_length_adjustment - Adjusts frame length if required * @dwc3: Pointer to our controller context structure @@ -592,6 +685,8 @@ static int dwc3_core_init(struct dwc3 *dwc) dwc3_frame_length_adjustment(dwc, dwc->fladj);
#if CONFIG_IS_ENABLED(OF_CONTROL) + dwc3_set_incr_burst_type(dwc); + /* * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not * reliably support Rx Detect in P3 mode(P3 is the default diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index e28001a..727e667 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -139,6 +139,17 @@
/* Bit fields */
+/* Global SoC Bus Configuration INCRx Register 0 */ +#define DWC3_GSBUSCFG0_INCR256BRSTENA BIT(7) /* INCR256 burst */ +#define DWC3_GSBUSCFG0_INCR128BRSTENA BIT(6) /* INCR128 burst */ +#define DWC3_GSBUSCFG0_INCR64BRSTENA BIT(5) /* INCR64 burst */ +#define DWC3_GSBUSCFG0_INCR32BRSTENA BIT(4) /* INCR32 burst */ +#define DWC3_GSBUSCFG0_INCR16BRSTENA BIT(3) /* INCR16 burst */ +#define DWC3_GSBUSCFG0_INCR8BRSTENA BIT(2) /* INCR8 burst */ +#define DWC3_GSBUSCFG0_INCR4BRSTENA BIT(1) /* INCR4 burst */ +#define DWC3_GSBUSCFG0_INCRBRSTENA BIT(0) /* undefined length enable */ +#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff + /* Global Configuration Register */ #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) #define DWC3_GCTL_U2RSTECN (1 << 16) @@ -857,6 +868,8 @@ struct dwc3 { struct list_head list; };
+#define INCRX_BURST_MODE 0 +#define INCRX_UNDEF_LENGTH_BURST_MODE 1 /* -------------------------------------------------------------------------- */
/* -------------------------------------------------------------------------- */