Signed-off-by: Marek Vasut marex@denx.de Cc: Stefano Babic sbabic@denx.de Cc: Albert ARIBAUD albert.u.boot@aribaud.net --- arch/arm/cpu/arm926ejs/cache.c | 17 ++++++++--------- 1 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 0b36294..1d3dc6e 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -30,7 +30,7 @@
void invalidate_dcache_all(void) { - asm volatile("mcr p15, 0, %0, c7, c6, 0\n"::"r"(0)); + asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0)); }
void flush_dcache_all(void) @@ -40,7 +40,7 @@ void flush_dcache_all(void) "mrc p15, 0, r15, c7, c14, 3\n" "bne 0b\n" "mcr p15, 0, %0, c7, c10, 4\n" - ::"r"(0):"memory" + : : "r"(0) : "memory" ); }
@@ -67,7 +67,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) return;
while (start < stop) { - asm volatile("mcr p15, 0, %0, c7, c6, 1\n"::"r"(start)); + asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start)); start += CONFIG_SYS_CACHELINE_SIZE; } } @@ -78,11 +78,11 @@ void flush_dcache_range(unsigned long start, unsigned long stop) return;
while (start < stop) { - asm volatile("mcr p15, 0, %0, c7, c14, 1\n"::"r"(start)); + asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start)); start += CONFIG_SYS_CACHELINE_SIZE; }
- asm volatile("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0)); + asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0)); }
void flush_cache(unsigned long start, unsigned long size) @@ -114,8 +114,7 @@ void flush_cache(unsigned long start, unsigned long size) /* * Stub implementations for l2 cache operations */ -void __l2_cache_disable(void) -{ -} +void __l2_cache_disable(void) {} + void l2_cache_disable(void) - __attribute__((weak, alias("__l2_cache_disable"))); + __attribute__((weak, alias("__l2_cache_disable")));