Align microblaze with the other architectures and provide an implementation for flush_dcache_range(). Also, remove the microblaze exception in drivers/core/device.c.
Signed-off-by: Ovidiu Panait ovpanait@gmail.com ---
arch/microblaze/cpu/cache.c | 8 ++++++++ drivers/core/device.c | 5 ----- 2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index 60b6d549d7..cce33a6eb5 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -43,6 +43,14 @@ static void __flush_dcache(ulong addr, ulong size) } }
+void flush_dcache_range(unsigned long start, unsigned long end) +{ + if (start >= end) + return; + + __flush_dcache(start, end - start); +} + void flush_dcache_all(void) { __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DEFAULT_CACHE_SIZE); diff --git a/drivers/core/device.c b/drivers/core/device.c index 1b356f12dd..16f808f2be 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -328,13 +328,8 @@ static void *alloc_priv(int size, uint flags) * within this range at the start. The driver can then * use normal flush-after-write, invalidate-before-read * procedures. - * - * TODO(sjg@chromium.org): Drop this microblaze - * exception. */ -#ifndef CONFIG_MICROBLAZE flush_dcache_range((ulong)priv, (ulong)priv + size); -#endif } } else { priv = calloc(1, size);