From: Sieu Mun Tang sieu.mun.tang@intel.com
Enable dtb build for QSPI Arria 10 SoCDK.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Signed-off-by: Sieu Mun Tang sieu.mun.tang@intel.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_arria10_socdk_qspi.dts | 63 +++ .../socfpga_arria10_socdk_qspi_handoff.dtsi | 522 ++++++++++++++++++ 3 files changed, 586 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi.dts create mode 100644 arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7330121dba..2534b1c9ad 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -427,6 +427,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3_270_3.dtb \ socfpga_arria10_chameleonv3_480_2.dtb \ + socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_is1.dtb \ diff --git a/arch/arm/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/dts/socfpga_arria10_socdk_qspi.dts new file mode 100644 index 0000000000..cf11d6b3bc --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_socdk_qspi.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright (C) 2019 Intel Corporation + * + * These codes were based on handoffs + * generated from both Qsys and Quartus. + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" +#include "socfpga_arria10_socdk-u-boot.dtsi" +#include "socfpga_arria10_handoff_u-boot.dtsi" +#include "socfpga_arria10_socdk_qspi_handoff.dtsi" + +/ { + aliases { + spi0 = &qspi; + }; + + fs_loader0: fs-loader { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + sfconfig = <0 0 100000000 3>; + }; +}; + +&fpga_mgr { + u-boot,dm-pre-reloc; + firmware-loader = <&fs_loader0>; + altr,bitstream = "300000"; +}; + +&l4_main_clk { + u-boot,dm-pre-reloc; +}; + +&qspi_clk { + u-boot,dm-pre-reloc; +}; + +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; + + flash0: n25q00a@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.dtsi b/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.dtsi new file mode 100644 index 0000000000..eff15b494a --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_socdk_qspi_handoff.dtsi @@ -0,0 +1,522 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright (C) 2019 Intel Corporation + * + * These codes were based on handoffs + * generated from both Qsys and Quartus. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "SOCFPGA Arria10 Dev Kit"; /* Bootloader setting: uboot.model */ + + /* Clock sources */ + clocks { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + + /* Clock source: altera_arria10_hps_eosc1 */ + altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "altera_arria10_hps_eosc1-clk"; + }; + + /* Clock source: altera_arria10_hps_cb_intosc_ls */ + altera_arria10_hps_cb_intosc_ls: + altera_arria10_hps_cb_intosc_ls { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <60000000>; + clock-output-names = + "altera_arria10_hps_cb_intosc_ls-clk"; + }; + + /* Clock source: altera_arria10_hps_f2h_free */ + altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "altera_arria10_hps_f2h_free-clk"; + }; + }; + + /* + * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver + * Version: 1.0 + * Binding: device + */ + i_clk_mgr: clock_manager@0xffd04000 { + compatible = "altr,socfpga-a10-clk-init"; + reg = <0xffd04000 0x00000200>; + reg-names = "soc_clock_manager_OCP_SLV"; + + /* + * Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp + */ + mainpll { + /* Field: vco0.psrc */ + vco0-psrc = <0>; + /* Field: vco1.denom */ + vco1-denom = <1>; + /* Field: vco1.numer */ + vco1-numer = <191>; + /* Field: mpuclk.cnt */ + mpuclk-cnt = <0>; + /* Field: mpuclk.src */ + mpuclk-src = <0>; + /* Field: nocclk.cnt */ + nocclk-cnt = <0>; + /* Field: nocclk.src */ + nocclk-src = <0>; + /* Field: cntr2clk.cnt */ + cntr2clk-cnt = <900>; + /* Field: cntr3clk.cnt */ + cntr3clk-cnt = <900>; + /* Field: cntr4clk.cnt */ + cntr4clk-cnt = <900>; + /* Field: cntr5clk.cnt */ + cntr5clk-cnt = <900>; + /* Field: cntr6clk.cnt */ + cntr6clk-cnt = <900>; + /* Field: cntr7clk.cnt */ + cntr7clk-cnt = <900>; + /* Field: cntr7clk.src */ + cntr7clk-src = <0>; + /* Field: cntr8clk.cnt */ + cntr8clk-cnt = <900>; + /* Field: cntr9clk.cnt */ + cntr9clk-cnt = <900>; + /* Field: cntr9clk.src */ + cntr9clk-src = <0>; + /* Field: cntr15clk.cnt */ + cntr15clk-cnt = <900>; + /* Field: nocdiv.l4mainclk */ + nocdiv-l4mainclk = <0>; + /* Field: nocdiv.l4mpclk */ + nocdiv-l4mpclk = <0>; + /* Field: nocdiv.l4spclk */ + nocdiv-l4spclk = <2>; + /* Field: nocdiv.csatclk */ + nocdiv-csatclk = <0>; + /* Field: nocdiv.cstraceclk */ + nocdiv-cstraceclk = <1>; + /* Field: nocdiv.cspdbgclk */ + nocdiv-cspdbgclk = <1>; + }; + + /* + * Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp + */ + perpll { + /* Field: vco0.psrc */ + vco0-psrc = <0>; + /* Field: vco1.denom */ + vco1-denom = <1>; + /* Field: vco1.numer */ + vco1-numer = <159>; + /* Field: cntr2clk.cnt */ + cntr2clk-cnt = <7>; + /* Field: cntr2clk.src */ + cntr2clk-src = <1>; + /* Field: cntr3clk.cnt */ + cntr3clk-cnt = <900>; + /* Field: cntr3clk.src */ + cntr3clk-src = <1>; + /* Field: cntr4clk.cnt */ + cntr4clk-cnt = <19>; + /* Field: cntr4clk.src */ + cntr4clk-src = <1>; + /* Field: cntr5clk.cnt */ + cntr5clk-cnt = <499>; + /* Field: cntr5clk.src */ + cntr5clk-src = <1>; + /* Field: cntr6clk.cnt */ + cntr6clk-cnt = <900>; + /* Field: cntr6clk.src */ + cntr6clk-src = <1>; + /* Field: cntr7clk.cnt */ + cntr7clk-cnt = <900>; + /* Field: cntr8clk.cnt */ + cntr8clk-cnt = <900>; + /* Field: cntr8clk.src */ + cntr8clk-src = <0>; + /* Field: cntr9clk.cnt */ + cntr9clk-cnt = <900>; + /* Field: emacctl.emac0sel */ + emacctl-emac0sel = <0>; + /* Field: emacctl.emac1sel */ + emacctl-emac1sel = <0>; + /* Field: emacctl.emac2sel */ + emacctl-emac2sel = <0>; + /* Field: gpiodiv.gpiodbclk */ + gpiodiv-gpiodbclk = <32000>; + }; + + /* + * Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp + */ + alteragrp { + /* Register: nocclk */ + nocclk = <0x0384000b>; + /* Register: mpuclk */ + mpuclk = <0x03840001>; + }; + }; + + /* + * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver + * Version: 1.0 + * Binding: pinmux + */ + i_io48_pin_mux: pinmux@0xffd07000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "pinctrl-single"; + reg = <0xffd07000 0x00000800>; + reg-names = "soc_3v_io48_pin_mux_OCP_SLV"; + + /* + * Address Block: + * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp + */ + shared { + reg = <0xffd07000 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + /* Register: pinmux_shared_io_q1_1 */ + <0x00000000 0x00000008>, + /* Register: pinmux_shared_io_q1_2 */ + <0x00000004 0x00000008>, + /* Register: pinmux_shared_io_q1_3 */ + <0x00000008 0x00000008>, + /* Register: pinmux_shared_io_q1_4 */ + <0x0000000c 0x00000008>, + /* Register: pinmux_shared_io_q1_5 */ + <0x00000010 0x00000008>, + /* Register: pinmux_shared_io_q1_6 */ + <0x00000014 0x00000008>, + /* Register: pinmux_shared_io_q1_7 */ + <0x00000018 0x00000008>, + /* Register: pinmux_shared_io_q1_8 */ + <0x0000001c 0x00000008>, + /* Register: pinmux_shared_io_q1_9 */ + <0x00000020 0x00000008>, + /* Register: pinmux_shared_io_q1_10 */ + <0x00000024 0x00000008>, + /* Register: pinmux_shared_io_q1_11 */ + <0x00000028 0x00000008>, + /* Register: pinmux_shared_io_q1_12 */ + <0x0000002c 0x00000008>, + /* Register: pinmux_shared_io_q2_1 */ + <0x00000030 0x00000004>, + /* Register: pinmux_shared_io_q2_2 */ + <0x00000034 0x00000004>, + /* Register: pinmux_shared_io_q2_3 */ + <0x00000038 0x00000004>, + /* Register: pinmux_shared_io_q2_4 */ + <0x0000003c 0x00000004>, + /* Register: pinmux_shared_io_q2_5 */ + <0x00000040 0x00000004>, + /* Register: pinmux_shared_io_q2_6 */ + <0x00000044 0x00000004>, + /* Register: pinmux_shared_io_q2_7 */ + <0x00000048 0x00000004>, + /* Register: pinmux_shared_io_q2_8 */ + <0x0000004c 0x00000004>, + /* Register: pinmux_shared_io_q2_9 */ + <0x00000050 0x00000004>, + /* Register: pinmux_shared_io_q2_10 */ + <0x00000054 0x00000004>, + /* Register: pinmux_shared_io_q2_11 */ + <0x00000058 0x00000004>, + /* Register: pinmux_shared_io_q2_12 */ + <0x0000005c 0x00000004>, + /* Register: pinmux_shared_io_q3_1 */ + <0x00000060 0x00000003>, + /* Register: pinmux_shared_io_q3_2 */ + <0x00000064 0x00000003>, + /* Register: pinmux_shared_io_q3_3 */ + <0x00000068 0x00000003>, + /* Register: pinmux_shared_io_q3_4 */ + <0x0000006c 0x00000003>, + /* Register: pinmux_shared_io_q3_5 */ + <0x00000070 0x00000003>, + /* Register: pinmux_shared_io_q3_6 */ + <0x00000074 0x0000000f>, + /* Register: pinmux_shared_io_q3_7 */ + <0x00000078 0x0000000a>, + /* Register: pinmux_shared_io_q3_8 */ + <0x0000007c 0x0000000a>, + /* Register: pinmux_shared_io_q3_9 */ + <0x00000080 0x0000000a>, + /* Register: pinmux_shared_io_q3_10 */ + <0x00000084 0x0000000a>, + /* Register: pinmux_shared_io_q3_11 */ + <0x00000088 0x00000001>, + /* Register: pinmux_shared_io_q3_12 */ + <0x0000008c 0x00000001>, + /* Register: pinmux_shared_io_q4_1 */ + <0x00000090 0x00000000>, + /* Register: pinmux_shared_io_q4_2 */ + <0x00000094 0x00000000>, + /* Register: pinmux_shared_io_q4_3 */ + <0x00000098 0x0000000f>, + /* Register: pinmux_shared_io_q4_4 */ + <0x0000009c 0x0000000c>, + /* Register: pinmux_shared_io_q4_5 */ + <0x000000a0 0x0000000f>, + /* Register: pinmux_shared_io_q4_6 */ + <0x000000a4 0x0000000f>, + /* Register: pinmux_shared_io_q4_7 */ + <0x000000a8 0x0000000a>, + /* Register: pinmux_shared_io_q4_8 */ + <0x000000ac 0x0000000a>, + /* Register: pinmux_shared_io_q4_9 */ + <0x000000b0 0x0000000c>, + /* Register: pinmux_shared_io_q4_10 */ + <0x000000b4 0x0000000c>, + /* Register: pinmux_shared_io_q4_11 */ + <0x000000b8 0x0000000c>, + /* Register: pinmux_shared_io_q4_12 */ + <0x000000bc 0x0000000c>; + }; + + /* + * Address Block: + * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp + */ + dedicated { + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + pinctrl-single,pins = + /* Register: pinmux_dedicated_io_4 */ + <0x0000000c 0x00000004>, + /* Register: pinmux_dedicated_io_5 */ + <0x00000010 0x00000004>, + /* Register: pinmux_dedicated_io_6 */ + <0x00000014 0x00000004>, + /* Register: pinmux_dedicated_io_7 */ + <0x00000018 0x00000004>, + /* Register: pinmux_dedicated_io_8 */ + <0x0000001c 0x00000004>, + /* Register: pinmux_dedicated_io_9 */ + <0x00000020 0x00000004>, + /* Register: pinmux_dedicated_io_10 */ + <0x00000024 0x0000000a>, + /* Register: pinmux_dedicated_io_11 */ + <0x00000028 0x0000000a>, + /* Register: pinmux_dedicated_io_12 */ + <0x0000002c 0x0000000a>, + /* Register: pinmux_dedicated_io_13 */ + <0x00000030 0x0000000a>, + /* Register: pinmux_dedicated_io_14 */ + <0x00000034 0x0000000a>, + /* Register: pinmux_dedicated_io_15 */ + <0x00000038 0x0000000a>, + /* Register: pinmux_dedicated_io_16 */ + <0x0000003c 0x0000000d>, + /* Register: pinmux_dedicated_io_17 */ + <0x00000040 0x0000000d>; + }; + + /* + * Address Block: + * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp + */ + dedicated_cfg { + reg = <0xffd07200 0x00000200>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x003f3f3f>; + pinctrl-single,pins = + /* Register: configuration_dedicated_io_bank */ + <0x00000100 0x00000101>, + /* Register: configuration_dedicated_io_1 */ + <0x00000104 0x000b080a>, + /* Register: configuration_dedicated_io_2 */ + <0x00000108 0x000b080a>, + /* Register: configuration_dedicated_io_3 */ + <0x0000010c 0x000b080a>, + /* Register: configuration_dedicated_io_4 */ + <0x00000110 0x0008282a>, + /* Register: configuration_dedicated_io_5 */ + <0x00000114 0x000a282a>, + /* Register: configuration_dedicated_io_6 */ + <0x00000118 0x0008282a>, + /* Register: configuration_dedicated_io_7 */ + <0x0000011c 0x000a282a>, + /* Register: configuration_dedicated_io_8 */ + <0x00000120 0x000a282a>, + /* Register: configuration_dedicated_io_9 */ + <0x00000124 0x000a282a>, + /* Register: configuration_dedicated_io_10 */ + <0x00000128 0x00090000>, + /* Register: configuration_dedicated_io_11 */ + <0x0000012c 0x00090000>, + /* Register: configuration_dedicated_io_12 */ + <0x00000130 0x00090000>, + /* Register: configuration_dedicated_io_13 */ + <0x00000134 0x00090000>, + /* Register: configuration_dedicated_io_14 */ + <0x00000138 0x00090000>, + /* Register: configuration_dedicated_io_15 */ + <0x0000013c 0x00090000>, + /* Register: configuration_dedicated_io_16 */ + <0x00000140 0x0008282a>, + /* Register: configuration_dedicated_io_17 */ + <0x00000144 0x000a282a>; + }; + + /* + * Address Block: + * soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp + */ + fpga { + reg = <0xffd07400 0x00000100>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000001>; + pinctrl-single,pins = + /* Register: pinmux_emac0_usefpga */ + <0x00000000 0x00000000>, + /* Register: pinmux_emac1_usefpga */ + <0x00000004 0x00000000>, + /* Register: pinmux_emac2_usefpga */ + <0x00000008 0x00000000>, + /* Register: pinmux_i2c0_usefpga */ + <0x0000000c 0x00000000>, + /* Register: pinmux_i2c1_usefpga */ + <0x00000010 0x00000000>, + /* Register: pinmux_i2c_emac0_usefpga */ + <0x00000014 0x00000000>, + /* Register: pinmux_i2c_emac1_usefpga */ + <0x00000018 0x00000000>, + /* Register: pinmux_i2c_emac2_usefpga */ + <0x0000001c 0x00000000>, + /* Register: pinmux_nand_usefpga */ + <0x00000020 0x00000000>, + /* Register: pinmux_qspi_usefpga */ + <0x00000024 0x00000000>, + /* Register: pinmux_sdmmc_usefpga */ + <0x00000028 0x00000000>, + /* Register: pinmux_spim0_usefpga */ + <0x0000002c 0x00000000>, + /* Register: pinmux_spim1_usefpga */ + <0x00000030 0x00000000>, + /* Register: pinmux_spis0_usefpga */ + <0x00000034 0x00000000>, + /* Register: pinmux_spis1_usefpga */ + <0x00000038 0x00000000>, + /* Register: pinmux_uart0_usefpga */ + <0x0000003c 0x00000000>, + /* Register: pinmux_uart1_usefpga */ + <0x00000040 0x00000000>; + }; + }; + + /* + * Driver: altera_arria10_soc_noc_arria10_uboot_driver + * Version: 1.0 + * Binding: device + */ + i_noc: noc@0xffd10000 { + compatible = "altr,socfpga-a10-noc"; + reg = <0xffd10000 0x00008000>; + reg-names = "mpu_m0"; + + firewall { + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver. + * I_NOC.mpu_m0. + * noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * mpuregion0addr.limit + */ + mpu0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit + */ + l3-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram0region0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram0region0addr.limit + */ + fpga2sdram0-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram1region0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram1region0addr.limit + */ + fpga2sdram1-0 = <0x00000000 0x0000ffff>; + /* + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram2region0addr.base + * + * Driver setting: + * altera_arria10_soc_noc_arria10_uboot_driver.I_NOC. + * mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr. + * fpga2sdram2region0addr.limit + */ + fpga2sdram2-0 = <0x00000000 0x0000ffff>; + }; + }; + + hps_fpgabridge0: fpgabridge@0 { + compatible = "altr,socfpga-hps2fpga-bridge"; + init-val = <1>; + }; + + hps_fpgabridge1: fpgabridge@1 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + init-val = <1>; + }; + + hps_fpgabridge2: fpgabridge@2 { + compatible = "altr,socfpga-fpga2hps-bridge"; + init-val = <1>; + }; + + hps_fpgabridge3: fpgabridge@3 { + compatible = "altr,socfpga-fpga2sdram0-bridge"; + init-val = <1>; + }; + + hps_fpgabridge4: fpgabridge@4 { + compatible = "altr,socfpga-fpga2sdram1-bridge"; + init-val = <0>; + }; + + hps_fpgabridge5: fpgabridge@5 { + compatible = "altr,socfpga-fpga2sdram2-bridge"; + init-val = <1>; + }; +};