On 2/7/23 10:21, Andre Przywara wrote:
Hi,
to trigger the actual semihosting action in the debugger, we used some carefully constructed inline assembly sequence. This was motivated by the trigger being really just a single instruction, so originally this could be neatly inlined by the compiler. However we now have a separate function anyway, so inlining is no longer happening. On top of that the inline assembly was really fragile and hard to read.
To clean that up, just use actual assembly functions, which does away with all the tricks to force the compiler into submission. Patch 1 is for ARM, patch 2 for RISC-V. Briefly tested on arm and aarch64 QEMU, and on an ARMv8 fastmodel, plus compile-tested for RISC-V. Please test it on your system!
Cheers, Andre
P.S. This idea came up before, but I don't remember if patches were floating around already. If there were, apologies for my ignorance, and I will be all too happy to use those patches instead of mine here, just point me to them.
Andre Przywara (2): arm: semihosting: replace inline assembly with assembly file riscv: semihosting: replace inline assembly with assembly file
arch/arm/lib/semihosting.S | 31 ++++++++++++++++++++++++ arch/arm/lib/semihosting.c | 47 ------------------------------------ arch/riscv/lib/semihosting.S | 22 +++++++++++++++++ arch/riscv/lib/semihosting.c | 24 ------------------ 4 files changed, 53 insertions(+), 71 deletions(-) create mode 100644 arch/arm/lib/semihosting.S delete mode 100644 arch/arm/lib/semihosting.c create mode 100644 arch/riscv/lib/semihosting.S delete mode 100644 arch/riscv/lib/semihosting.c
I would like to test this, but I don't think I'll have time for a bit.
--Sean