The patch adds initial support for the Freescale mx51evk board. Network (FEC) and SD controller (fsl_esdhc) are supported.
Signed-off-by: Stefano Babic sbabic@denx.de Signed-off-by: Fred Fan fanyefeng@gmail.com --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 8 + board/freescale/mx51evk/Makefile | 48 ++++ board/freescale/mx51evk/config.mk | 15 ++ board/freescale/mx51evk/imximage.cfg | 119 ++++++++++ board/freescale/mx51evk/mx51evk.c | 418 ++++++++++++++++++++++++++++++++++ board/freescale/mx51evk/mx51evk.h | 49 ++++ include/configs/mx51evk.h | 185 +++++++++++++++ 9 files changed, 847 insertions(+), 0 deletions(-) create mode 100644 board/freescale/mx51evk/Makefile create mode 100644 board/freescale/mx51evk/config.mk create mode 100644 board/freescale/mx51evk/imximage.cfg create mode 100644 board/freescale/mx51evk/mx51evk.c create mode 100644 board/freescale/mx51evk/mx51evk.h create mode 100644 include/configs/mx51evk.h
diff --git a/MAINTAINERS b/MAINTAINERS index 9734b1d..8637550 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -151,6 +151,10 @@ Dave Ellis DGE@sixnetio.com
SXNI855T MPC8xx
+Fred Fan fanyefeng@gmail.com + + mx51evk i.MX51 + Thomas Frieden ThomasF@hyperion-entertainment.com
AmigaOneG3SE MPC7xx diff --git a/MAKEALL b/MAKEALL index ab1bb6f..485107a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -617,6 +617,7 @@ LIST_ARM11=" \ ######################################################################### LIST_ARM_CORTEX_A8=" \ devkit8000 \ + mx51evk \ omap3_beagle \ omap3_overo \ omap3_evm \ diff --git a/Makefile b/Makefile index ed6156f..01bf9a2 100644 --- a/Makefile +++ b/Makefile @@ -324,6 +324,10 @@ $(obj)u-boot.img: $(obj)u-boot.bin sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -d $< $@
+$(obj)u-boot.imx: $(obj)u-boot.bin + $(obj)tools/mkimage -n $(IMX_CONFIG) -T imximage \ + -e $(TEXT_BASE) -d $< $@ + $(obj)u-boot.kwb: $(obj)u-boot.bin $(obj)tools/mkimage -n $(KWD_CONFIG) -T kwbimage \ -a $(TEXT_BASE) -e $(TEXT_BASE) -d $< $@ @@ -3263,6 +3267,9 @@ mx31pdk_nand_config : unconfig fi @$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31
+mx51evk_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51evk freescale mx51 + omap2420h4_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 ti omap24xx
@@ -3729,6 +3736,7 @@ clobber: clean $(obj)cscope.* $(obj)*.*~ @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) @rm -f $(obj)u-boot.kwb + @rm -f $(obj)u-boot.imx @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes} @rm -f $(obj)cpu/mpc824x/bedbug_603e.c @rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm diff --git a/board/freescale/mx51evk/Makefile b/board/freescale/mx51evk/Makefile new file mode 100644 index 0000000..eb12fc5 --- /dev/null +++ b/board/freescale/mx51evk/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de +# +# (C) Copyright 2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx51evk.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx51evk/config.mk b/board/freescale/mx51evk/config.mk new file mode 100644 index 0000000..fecfd5e --- /dev/null +++ b/board/freescale/mx51evk/config.mk @@ -0,0 +1,15 @@ +# +# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. +# + +# +# The code contained herein is licensed under the GNU General Public +# License. You may obtain a copy of the GNU General Public License +# Version 2 or later at the following locations: +# +# http://www.opensource.org/licenses/gpl-license.html +# http://www.gnu.org/copyleft/gpl.html +# +LDSCRIPT = cpu/$(CPU)/$(SOC)/u-boot.lds +TEXT_BASE = 0x97800000 +IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg new file mode 100644 index 0000000..8d13567 --- /dev/null +++ b/board/freescale/mx51evk/imximage.cfg @@ -0,0 +1,119 @@ +# +# (C Copyright 2009 +# Stefano Babic DENX Software Engineering sbabic@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# Boot Device : one of +# spi_flash, nand, onenand, sd_card + +BOOT_FROM spi + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register + +# Setting IOMUXC +DATA 4 0x73FA88a0 0x200 +DATA 4 0x73FA850c 0x20c5 +DATA 4 0x73FA8510 0x20c5 +DATA 4 0x73FA883c 0x2 +DATA 4 0x73FA8848 0x2 +DATA 4 0x73FA84b8 0xe7 +DATA 4 0x73FA84bc 0x45 +DATA 4 0x73FA84c0 0x45 +DATA 4 0x73FA84c4 0x45 +DATA 4 0x73FA84c8 0x45 +DATA 4 0x73FA8820 0x0 +DATA 4 0x73FA84a4 0x3 +DATA 4 0x73FA84a8 0x3 +DATA 4 0x73FA84ac 0xe3 +DATA 4 0x73FA84b0 0xe3 +DATA 4 0x73FA84b4 0xe3 +DATA 4 0x73FA84cc 0xe3 +DATA 4 0x73FA84d0 0xe2 + +DATA 4 0x73FA882c 0x6 +DATA 4 0x73FA88a4 0x6 +DATA 4 0x73FA88ac 0x6 +DATA 4 0x73FA88b8 0x6 + +# Setting DDR for micron +# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model +# CAS=3 BL=4 +# ESDCTL_ESDCTL0 +DATA 4 0x83FD9000 0x82a20000 +# ESDCTL_ESDCTL1 +DATA 4 0x83FD9008 0x82a20000 +# ESDCTL_ESDMISC +DATA 4 0x83FD9010 0x000ad0d0 +# ESDCTL_ESDCFG0 +DATA 4 0x83FD9004 0x333574aa +# ESDCTL_ESDCFG1 +DATA 4 0x83FD900C 0x333574aa + +# Init DRAM on CS0 +# ESDCTL_ESDSCR +DATA 4 0x83FD9014 0x04008008 +DATA 4 0x83FD9014 0x0000801a +DATA 4 0x83FD9014 0x0000801b +DATA 4 0x83FD9014 0x00448019 +DATA 4 0x83FD9014 0x07328018 +DATA 4 0x83FD9014 0x04008008 +DATA 4 0x83FD9014 0x00008010 +DATA 4 0x83FD9014 0x00008010 +DATA 4 0x83FD9014 0x06328018 +DATA 4 0x83FD9014 0x03808019 +DATA 4 0x83FD9014 0x00408019 +DATA 4 0x83FD9014 0x00008000 + +# Init DRAM on CS1 +DATA 4 0x83FD9014 0x0400800c +DATA 4 0x83FD9014 0x0000801e +DATA 4 0x83FD9014 0x0000801f +DATA 4 0x83FD9014 0x0000801d +DATA 4 0x83FD9014 0x0732801c +DATA 4 0x83FD9014 0x0400800c +DATA 4 0x83FD9014 0x00008014 +DATA 4 0x83FD9014 0x00008014 +DATA 4 0x83FD9014 0x0632801c +DATA 4 0x83FD9014 0x0380801d +DATA 4 0x83FD9014 0x0040801d +DATA 4 0x83FD9014 0x00008004 + +# Write to CTL0 +DATA 4 0x83FD9000 0xb2a20000 +# Write to CTL1 +DATA 4 0x83FD9008 0xb2a20000 +# ESDMISC +DATA 4 0x83FD9010 0x000ad6d0 +#ESDCTL_ESDCDLYGD +DATA 4 0x83FD9034 0x90000000 +DATA 4 0x83FD9014 0x00000000 diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c new file mode 100644 index 0000000..dbf959d --- /dev/null +++ b/board/freescale/mx51evk/mx51evk.c @@ -0,0 +1,418 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx51_pins.h> +#include <asm/arch/iomux.h> +#include <asm/errno.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include "mx51evk.h" + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; +struct io_board_ctrl *mx51_io_board; + +u32 get_board_rev(void) +{ + return system_rev; +} + +static inline void setup_soc_rev(void) +{ + int reg; + + reg = __raw_readl(ROM_SI_REV); + switch (reg) { + case 0x02: + system_rev = 0x51000 | CHIP_REV_1_1; + break; + case 0x10: + if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) + system_rev = 0x51000 | CHIP_REV_2_5; + else + system_rev = 0x51000 | CHIP_REV_2_0; + break; + default: + system_rev = 0x51000 | CHIP_REV_1_0; + break; + } +} + +static inline void set_board_rev(int rev) +{ + system_rev |= (rev & 0xF) << 8; +} + +inline int is_soc_rev(int rev) +{ + return (system_rev & 0xFF) - rev; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + return 0; +} + +static void setup_uart(void) +{ + unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; + + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); +} + +static void setup_expio(void) +{ + u32 reg; + + /* CS5 setup */ + mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0); + writel(0x00410089, WEIM_BASE_ADDR + 0x78 + CSGCR1); + writel(0x00000002, WEIM_BASE_ADDR + 0x78 + CSGCR2); + /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ + writel(0x32260000, WEIM_BASE_ADDR + 0x78 + CSRCR1); + /* APR = 0 */ + writel(0x00000000, WEIM_BASE_ADDR + 0x78 + CSRCR2); + /* + * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, + * WCSA=0, WCSN=0 + */ + writel(0x72080F00, WEIM_BASE_ADDR + 0x78 + CSWCR1); + + mx51_io_board = (struct io_board_ctrl *)(CS5_BASE_ADDR + + IO_BOARD_OFFSET); + if ((readw(&mx51_io_board->id1) == 0xAAAA) && + (readw(&mx51_io_board->id2) == 0x5555)) { + if (is_soc_rev(CHIP_REV_2_0) < 0) { + reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR); + reg = (reg & (~0x70000)) | 0x30000; + writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR); + /* make sure divider effective */ + while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0) + ; + writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR); + } + } else { + /* CS1 */ + writel(0x00410089, WEIM_BASE_ADDR + 0x18 + CSGCR1); + writel(0x00000002, WEIM_BASE_ADDR + 0x18 + CSGCR2); + /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ + writel(0x32260000, WEIM_BASE_ADDR + 0x18 + CSRCR1); + /* APR=0 */ + writel(0x00000000, WEIM_BASE_ADDR + 0x18 + CSRCR2); + /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, + * WEN=0, WCSA=0, WCSN=0 + */ + writel(0x72080F00, WEIM_BASE_ADDR + 0x18 + CSWCR1); + mx51_io_board = (struct io_board_ctrl *)(CS1_BASE_ADDR + + IO_BOARD_OFFSET); + } + + /* Reset interrupt status reg */ + writew(0x1F, &(mx51_io_board->int_rest)); + writew(0x00, &(mx51_io_board->int_rest)); + writew(0xFFFF, &(mx51_io_board->int_mask)); + + /* Reset the XUART and Ethernet controllers */ + reg = readw(&(mx51_io_board->sw_reset)); + reg |= 0x9; + writew(reg, &(mx51_io_board->sw_reset)); + reg &= ~0x9; + writew(reg, &(mx51_io_board->sw_reset)); +} + +static void setup_fec(void) +{ + /*FEC_MDIO*/ + mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD); + + /*FEC_MDC*/ + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004); + + /* FEC RDATA[3] */ + mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); + + /* FEC RDATA[2] */ + mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); + + /* FEC RDATA[1] */ + mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); + + /* FEC RDATA[0] */ + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); + + /* FEC TDATA[3] */ + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004); + + /* FEC TDATA[2] */ + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004); + + /* FEC TDATA[1] */ + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004); + + /* FEC TDATA[0] */ + mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004); + + /* FEC TX_EN */ + mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004); + + /* FEC TX_ER */ + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004); + + /* FEC TX_CLK */ + mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180); + + /* FEC TX_COL */ + mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); + + /* FEC RX_CLK */ + mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); + + /* FEC RX_CRS */ + mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180); + + /* FEC RX_ER */ + mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); + + /* FEC RX_DV */ + mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180); +} + +#ifdef CONFIG_NET_MULTI +int board_eth_init(bd_t *bis) +{ + int rc = -ENODEV; + +#ifdef CONFIG_FEC_MXC + rc = fecmxc_initialize(bis); +#endif + return rc; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +int get_mmc_cd(struct mmc *mmc) +{ + uint32_t reg_base = (uint32_t)mmc->priv; + int ret; + + if (reg_base == MMC_SDHC1_BASE_ADDR) { + ret = readl(GPIO1_BASE_ADDR) & 0x01; + } else { + ret = readl(GPIO1_BASE_ADDR) & 0x40; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + u32 interface_esdhc = 0; + s32 status = 0; + u32 esdhc_base_pointer; + + for (interface_esdhc = 0; interface_esdhc < CONFIG_SYS_FSL_ESDHC_NUM; interface_esdhc++) { + switch (interface_esdhc) { + case 0: + esdhc_base_pointer = MMC_SDHC1_BASE_ADDR; + + mxc_request_iomux(MX51_PIN_SD1_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD1_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_GPIO1_0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_0, + PAD_CTL_HYS_ENABLE); + mxc_request_iomux(MX51_PIN_GPIO1_1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_1, + PAD_CTL_HYS_ENABLE); + break; + case 1: + esdhc_base_pointer = MMC_SDHC2_BASE_ADDR; + + mxc_request_iomux(MX51_PIN_SD2_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_DATA0, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD2_DATA1, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD2_DATA2, + IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD2_DATA3, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD2_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | + PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_SD2_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_GPIO1_6, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_6, + PAD_CTL_HYS_ENABLE); + mxc_request_iomux(MX51_PIN_GPIO1_5, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_5, + PAD_CTL_HYS_ENABLE); + break; + } + status |= fsl_esdhc_initialize(bis, esdhc_base_pointer, get_mmc_cd); + } + return status; +} + +#endif + +int board_init(void) +{ + setup_soc_rev(); + + gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE; /* board id for linux */ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + setup_uart(); + setup_expio(); + setup_fec(); + return 0; +} + +int checkboard(void) +{ + puts("Board: MX51 BABBAGE "); + + switch (system_rev & 0xff) { + case CHIP_REV_3_0: + puts("3.0 ["); + break; + case CHIP_REV_2_5: + puts("2.5 ["); + break; + case CHIP_REV_2_0: + puts("2.0 ["); + break; + case CHIP_REV_1_1: + puts("1.1 ["); + break; + case CHIP_REV_1_0: + default: + puts("1.0 ["); + break; + } + + switch (__raw_readl(SRC_BASE_ADDR + 0x8)) { + case 0x0001: + puts("POR"); + break; + case 0x0009: + puts("RST"); + break; + case 0x0010: + case 0x0011: + puts("WDOG"); + break; + default: + puts("unknown"); + } + puts("]\n"); + return 0; +} + diff --git a/board/freescale/mx51evk/mx51evk.h b/board/freescale/mx51evk/mx51evk.h new file mode 100644 index 0000000..fec886d --- /dev/null +++ b/board/freescale/mx51evk/mx51evk.h @@ -0,0 +1,49 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __BOARD_FREESCALE_BOARD_MX51_BABBAGE_H__ +#define __BOARD_FREESCALE_BOARD_MX51_BABBAGE_H__ + +#ifndef __ASSEMBLY__ +struct io_board_ctrl { + u16 led_ctrl; /* 0x00 */ + u16 resv1[0x03]; + u16 sb_stat; /* 0x08 */ + u16 resv2[0x03]; + u16 int_stat; /* 0x10 */ + u16 resv3[0x07]; + u16 int_rest; /* 0x20 */ + u16 resv4[0x0B]; + u16 int_mask; /* 0x38 */ + u16 resv5[0x03]; + u16 id1; /* 0x40 */ + u16 resv6[0x03]; + u16 id2; /* 0x48 */ + u16 resv7[0x03]; + u16 version; /* 0x50 */ + u16 resv8[0x03]; + u16 id3; /* 0x58 */ + u16 resv9[0x03]; + u16 sw_reset; /* 0x60 */ +}; +#endif + +/* CPLD offsets */ +#define IO_BOARD_OFFSET (0x20000) +#define PBC_ID_AAAA (0x20040) +#define PBC_ID_5555 (0x20048) +#define PBC_INT_REST (0x20020) +#define PBC_INT_MASK (0x20038) +#define PBC_SW_RESET (0x20060) + +#endif /* __BOARD_FREESCALE_BOARD_MX51_BABBAGE_H__ */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h new file mode 100644 index 0000000..c8b2970 --- /dev/null +++ b/include/configs/mx51evk.h @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX51-3Stack Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> + + /* High Level Configuration Options */ +#define CONFIG_SYS_APCS_GNU +#define CONFIG_L2_OFF + +#define CONFIG_MX51 /* in a mx51 */ + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ +#define CONFIG_MX51_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX51_UART1 + +/* + * MMC Configs + * */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + +#define CONFIG_MMC + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot_addr=0xa0000000\0" \ + "uboot=u-boot.bin\0" \ + "loadaddr=0x90800000\0" \ + "bootargs_base=setenv bootargs console= tty console=ttymxc0,${baudrate}\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" + +/* + * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A + * controller inverted. The controller is capable of detecting and correcting + * this, but it needs 4 network packets for that. Which means, at startup, you + * will not receive answers to the first 4 packest, unless there have been some + * broadcasts on the network, or your board is on a hub. Reducing the ARP + * timeout from default 5 seconds to 200ms we speed up the initial TFTP + * transfer, should the user wish one, significantly. + */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "BBG U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START CSD0_BASE_ADDR +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_CMDLINE_EDITING + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_IS_NOWHERE + +#endif /* __CONFIG_H */