10 Jun
2022
10 Jun
'22
11:40 p.m.
On Tue, May 17, 2022 at 05:41:39PM +0900, Masahisa Kojima wrote:
There is a TX-FIFO and Shift Register empty(TFES) status bit in spi controller. This commit checks the TFES bit to wait the TX transfer completes.
Signed-off-by: Masahisa Kojima masahisa.kojima@linaro.org Signed-off-by: Satoru Okamoto okamoto.satoru@socionext.com Acked-by: Jassi Brar jaswinder.singh@linaro.org
Applied to u-boot/next, thanks!
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Tom