The BCH for OMAP3 is implemented as the linux kernel in 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c does.
The kernel states:
---8<--- The OMAP3 GPMC hardware BCH engine computes remainder polynomials, it does not provide automatic error location and correction: this step is implemented using the BCH library. --->8---
And we do so in u-boot.
This implementation uses the same layout for BCH8 but it is fix. The current provided layout does only work with 64 Byte OOB.
Signed-off-by: Andreas Bießmann andreas.devel@googlemail.com Cc: Tom Rini trini@ti.com Cc: Ilya Yanok ilya.yanok@cogentembedded.com Cc: Scott Wood scottwood@freescale.com --- This patch has some debug stuff in which should be cleaned up.
arch/arm/cpu/armv7/omap3/board.c | 8 +- drivers/mtd/nand/omap_gpmc.c | 216 +++++++++++++++++++++++++++++++++++++- lib/Makefile | 3 +- 3 files changed, 223 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index f3cd81a..22286c0 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -330,8 +330,10 @@ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const arg { if (argc != 2) goto usage; - if (strncmp(argv[1], "hw", 2) == 0) + if (strncmp(argv[1], "hw1", 3) == 0) omap_nand_switch_ecc(1); + else if (strncmp(argv[1], "hw2", 3) == 0) + omap_nand_switch_ecc(2); else if (strncmp(argv[1], "sw", 2) == 0) omap_nand_switch_ecc(0); else @@ -347,7 +349,9 @@ usage: U_BOOT_CMD( nandecc, 2, 1, do_switch_ecc, "switch OMAP3 NAND ECC calculation algorithm", - "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm" + "[hw1/hw2/sw] - Switch between NAND hardware (hw1 - 1bit hamming),\n" + "\tNAND hardware assisted BCH8 (hw2 - 8bit BCH)\n" + "\tor software (sw) ecc algorithm" );
#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */ diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index f1469d1..a5ab046 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -27,6 +27,7 @@ #include <asm/arch/mem.h> #include <asm/arch/omap_gpmc.h> #include <linux/mtd/nand_ecc.h> +#include <linux/bch.h> #include <linux/compiler.h> #include <nand.h>
@@ -234,12 +235,194 @@ static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) } }
+/* + * basic BCH8 support + */ +#ifdef CONFIG_NAND_OMAP_BCH8 +static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT; + +/* + * omap_init_hwecc_bch - Initialize the BCH Hardware ECC for NAND flash in + * GPMC controller + * @mtd: MTD device structure + * @mode: Read/Write mode + */ +static void omap_init_hwecc_bch(struct nand_chip *chip, int32_t mode) +{ + uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; + + /* Clear the ecc result registers, select ecc reg as 1 */ + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); + + /* + * When using BCH, sector size is hardcoded to 512 bytes. + * Here we are using wrapping mode 6 both for reading and writing, with: + * size0 = 0 (no additional protected byte in spare area) + * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) + */ + writel((32 << 22) | (0 << 12), &gpmc_cfg->ecc_size_config); + + /* BCH configuration */ + val = ((1 << 16) | /* enable BCH */ + (1 << 12) | /* set fix to BCH8 */ + (0x06 << 8) | /* wrap mode = 6 */ + (dev_width << 7) | /* bus width */ + (0 << 4) | /* number of sectors (we use 1 sector)*/ + (cs << 1) | /* ECC CS */ + (0x1)); /* enable ECC */ +// debug("set ECC_CONFIG = 0x%08x\n", val); + writel(val, &gpmc_cfg->ecc_config); +} + +/** + * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction + * @mtd: MTD device structure + * @mode: Read/Write mode + */ +static void omap_enable_hwecc_bch(struct mtd_info *mtd, int32_t mode) +{ + struct nand_chip *chip = mtd->priv; + + omap_init_hwecc_bch(chip, mode); + /* enable ecc */ + writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config); +} + +/* + * omap_ecc_disable - Disable H/W ECC calculation + * + * @mtd: MTD device structure + * + */ +static void omap_ecc_disable(struct mtd_info *mtd) +{ + writel((readl(&gpmc_cfg->ecc_config) & ~0x1), + &gpmc_cfg->ecc_config); +} + +/* + * omap_calculate_ecc_bch - Read BCH ECC result + * + * @mtd: MTD device structure + * @dat: The pointer to data on which ecc is computed (unused here) + * @ecc: The ECC output buffer + */ +static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, + uint8_t *ecc) +{ + int ret = 0; + size_t i; + unsigned long nsectors, val1, val2, val3, val4; + uint8_t *pecc = ecc; + + nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1; + + for (i = 0; i < nsectors; i++) { +#if 0 + debug("read res0 @%p, res1 @%p, res2 @%p, res4 @%p\n", + &gpmc_cfg->bch_result_0_3[i].bch_result_x[0], + &gpmc_cfg->bch_result_0_3[i].bch_result_x[1], + &gpmc_cfg->bch_result_0_3[i].bch_result_x[2], + &gpmc_cfg->bch_result_0_3[i].bch_result_x[3]); +#endif + + /* Read hw-computed remainder */ + val1 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[0]); + val2 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[1]); + val3 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[2]); + val4 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[3]); +// debug("val1 = 0x%08lx, val2 = 0x%08lx, val3 = 0x%08lx, val4 = 0x%08lx\n", val1, val2, val3, val4); + + /* + * Add constant polynomial to remainder, in order to get an ecc + * sequence of 0xFFs for a buffer filled with 0xFFs. + */ + *ecc++ = 0xef ^ (val4 & 0xFF); + *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF); + *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF); + *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF); + *ecc++ = 0xed ^ (val3 & 0xFF); + *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF); + *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF); + *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF); + *ecc++ = 0x97 ^ (val2 & 0xFF); + *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF); + *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF); + *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF); + *ecc++ = 0xb5 ^ (val1 & 0xFF); +#if 0 + debug("ecc: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + pecc[0], pecc[1], pecc[2], pecc[3], pecc[4], pecc[5], pecc[6], + pecc[7], pecc[8], pecc[9], pecc[10], pecc[11], pecc[12]); +#endif +} + + /* + * Stop reading anymore ECC vals and clear old results + * enable will be called if more reads are required + */ + omap_ecc_disable(mtd); + + return ret; +} + +/** + * omap_correct_data_bch - Decode received data and correct errors + * @mtd: MTD device structure + * @data: page data + * @read_ecc: ecc read from nand flash + * @calc_ecc: ecc read from HW ECC registers + */ +static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data, + u_char *read_ecc, u_char *calc_ecc) +{ + int i, count; + /* cannot correct more than 8 errors */ + unsigned int errloc[8]; + struct nand_chip *chip = mtd->priv; + struct bch_control *bch = chip->priv; + + count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc); + if (count > 0) { + /* correct errors */ + for (i = 0; i < count; i++) { + /* correct data only, not ecc bytes */ + if (errloc[i] < 8*512) + data[errloc[i]/8] ^= 1 << (errloc[i] & 7); + printf("corrected bitflip %u\n", errloc[i]); + debug("read_ecc: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + read_ecc[0], read_ecc[1], read_ecc[2], read_ecc[3], read_ecc[4], read_ecc[5], read_ecc[6], + read_ecc[7], read_ecc[8], read_ecc[9], read_ecc[10], read_ecc[11], read_ecc[12]); + debug("calc_ecc: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + calc_ecc[0], calc_ecc[1], calc_ecc[2], calc_ecc[3], calc_ecc[4], calc_ecc[5], calc_ecc[6], + calc_ecc[7], calc_ecc[8], calc_ecc[9], calc_ecc[10], calc_ecc[11], calc_ecc[12]); + } + } else if (count < 0) { + puts("ecc unrecoverable error\n"); + } + return count; +} + +/** + * omap_free_bch - Release BCH ecc resources + * @mtd: MTD device structure + */ +static void omap_free_bch(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + if (chip->priv) { + free_bch((struct bch_control *)chip->priv); + chip->priv = NULL; + } +} +#endif /* CONFIG_NAND_OMAP_BCH8 */ + #ifndef CONFIG_SPL_BUILD /* * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc. * The default is to come up on s/w ecc * - * @hardware - 1 -switch to h/w ecc, 0 - s/w ecc + * @hardware - 1 -switch to h/w ecc, 2 - switch to h/w assisted BCH8, 0 - s/w ecc * */ void omap_nand_switch_ecc(int32_t hardware) @@ -279,6 +462,18 @@ void omap_nand_switch_ecc(int32_t hardware) nand->ecc.calculate = omap_calculate_ecc; omap_hwecc_init(nand); printf("HW ECC selected\n"); +#ifdef CONFIG_NAND_OMAP_BCH8 + } else if (hardware == 2) { + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &hw_bch8_nand_oob; + nand->ecc.size = 512; + nand->ecc.bytes = 13; + nand->ecc.hwctl = omap_enable_hwecc_bch; + nand->ecc.correct = omap_correct_data_bch; + nand->ecc.calculate = omap_calculate_ecc_bch; + omap_init_hwecc_bch(nand, NAND_ECC_READ); + printf("HW BCH8 selected\n"); +#endif } else { nand->ecc.mode = NAND_ECC_SOFT; /* Use mtd default settings */ @@ -313,6 +508,7 @@ int board_nand_init(struct nand_chip *nand) { int32_t gpmc_config = 0; cs = 0; + nand->priv = NULL;
/* * xloader/Uboot's gpmc configuration would have configured GPMC for @@ -351,6 +547,23 @@ int board_nand_init(struct nand_chip *nand)
nand->chip_delay = 100; /* Default ECC mode */ +#ifdef CONFIG_NAND_OMAP_BCH8 + nand->priv = init_bch(13, 8, 0x201b /* hw polynominal */); + if (!nand->priv) { + puts("Could not init_bch()\n"); + } +#endif + +#if defined CONFIG_NAND_OMAP_BCH8 + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &hw_bch8_nand_oob; + nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; + nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; + nand->ecc.hwctl = omap_enable_hwecc_bch; + nand->ecc.correct = omap_correct_data_bch; + nand->ecc.calculate = omap_calculate_ecc_bch; + omap_init_hwecc_bch(nand, NAND_ECC_READ); +#else #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC) nand->ecc.mode = NAND_ECC_SOFT; #else @@ -363,6 +576,7 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.calculate = omap_calculate_ecc; omap_hwecc_init(nand); #endif +#endif
#ifdef CONFIG_SPL_BUILD if (nand->options & NAND_BUSWIDTH_16) diff --git a/lib/Makefile b/lib/Makefile index e44e045..20cc40c 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libgeneric.o
+COBJS-$(CONFIG_BCH) += bch.o + ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_ADDR_MAP) += addr_map.o -COBJS-$(CONFIG_BCH) += bch.o COBJS-$(CONFIG_AES) += aes.o COBJS-$(CONFIG_BZIP2) += bzlib.o COBJS-$(CONFIG_BZIP2) += bzlib_crctable.o