-----Original Message----- From: sun york-R58495 Sent: Wednesday, October 30, 2013 10:14 PM To: Jain Priyanka-B32167; u-boot@lists.denx.de Cc: Aggrwal Poonam-B10812 Subject: Re: [PATCH] powerpc/t1040qds: Add DDR Raw Timing support
On 10/25/2013 02:49 AM, Priyanka Jain wrote:
T1040QDS-D3 has dual-rank DDR: Micron, MT18KSF51272AZ-1G6 (4GB, x72, CL=10). Add Raw Timing structure for this DDR.
Typically SPD method is used for getting DDR parameter and calculating values for various DDR controller registers.
But somentimes it may happen that SPD present on DDR may get accidently erased or is not working properly during initial bring-up. In that circumnstance, DDR raw timing structure can be use as fallback option for getting DDR parameters.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com
I don't think it is appropriate to use raw timing for this application. This board use DIMMs, not soldered DDR chips. In normal cases, this piece of code is not used. It is only useful if you have a DIMM without a valid SPD. You could get another DIMM. I am not saying this patch is wrong, it is just useless for general public.
York
[Jain Priyanka-B32167] You are right that in case of DIMM type of memories, raw timing may not be required. But there are certain scenarios in which keeping raw timing is useful like 1)During initial bring-up, there is a possibility that I2C bus may be broken, In that case boot-loader has to rely on the fallback option of raw timing. 2)Also raw timings are used in emulator to test t1040. So, we prefer to keep raw timing as fallback option.
Regards Priyanka