On 27 January 2015 at 05:36, Przemyslaw Marczak p.marczak@samsung.com wrote:
Some versions of Exynos5 supports High-Speed I2C, on few interfaces, this change allows support this. The new flag is: PINMUX_FLAG_HS_MODE
Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Simon Glass sjg@chromium.org Cc: Akshay Saraswat akshay.s@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com
Changes v3:
- add new flag: PINMUX_FLAG_HS_MODE
arch/arm/cpu/armv7/exynos/pinmux.c | 27 +++++++++++++++++++-------- arch/arm/include/asm/arch-exynos/pinmux.h | 3 +++ 2 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 94d0297..be43e22 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -266,22 +266,33 @@ static void exynos5_sromc_config(int flags)
static void exynos5_i2c_config(int peripheral, int flags) {
int func01, func23;/* High-Speed I2C */if (flags & PINMUX_FLAG_HS_MODE) {func01 = 4;func23 = 4;} else {func01 = 2;func23 = 3;}switch (peripheral) { case PERIPH_ID_I2C0:
gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01));gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01)); break; case PERIPH_ID_I2C1:
gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01));gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01)); break; case PERIPH_ID_I2C2:
gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23));gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23)); break; case PERIPH_ID_I2C3:
gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23));gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23)); break; case PERIPH_ID_I2C4: gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h index 0b91ef6..d0ae757 100644 --- a/arch/arm/include/asm/arch-exynos/pinmux.h +++ b/arch/arm/include/asm/arch-exynos/pinmux.h @@ -23,6 +23,9 @@ enum { /* Flags for SROM controller */ PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
/* Flags for I2C */PINMUX_FLAG_HS_MODE = 1 << 1, /* I2C High Speed Mode */};
/**
Acked-by: Simon Glass sjg@chromium.org