Hi Jerry.
Ok, the good news is that eliminates one of the failure modes. We eliminate enough of them and the real one will be obvious. ;-) That was somewhat of a long shot, so it isn't too surprising that it wasn't the fault.
:-)
I'm not familiar with the 85xx processors, I presume they have BAT registers like most 8xxx family. Is it possible the memory is mapped via a BAT and _that_ is set up wrong (cached and/or doesn't have the "G" bit set)? BATs override the TLBs.
I just checked, because I wasn't sure, and according to the Reference Manual, the e500 core (e.g, the 8560) does not implement the BAT registers.
Does the TLB have the "G" (Guarded) bit set? That prevents out-of-order loading (probably not an issue, but something to check).
Yes, the guarded bit is set in .../board/sbc8560/init.S.
How about hitting it with da big hammer: put a sync;isync pair in the loop. If that makes it better, remove the isync (should not be necessary). If that still works, try using a eieio instead of the sync (I'm not sure if eieio is useful for the 85xx, on the 603e core, it is a NOP).
I thought I had tried this earlier, but couldn't remember. So I tried it again. No Luck. (The generated code does the sync/isync before the register fetch. If the FLG bit is still set, the sync/isync is done again and the fetch repeated.)
According to the RM, the e500 replaces eieio with mbar. Since I had not tried that one, I just did. You guessed it... no luck.
I'm probably doing something really stupid; and probably really simple which is why I haven't spotted *my* problem.
It is also possible the WR SBC8560 we have is broken. Although I think that is not a really likely because it runs the VxWorks bootloader fine.
- Mark
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