Convert register access to structure style, part #1.
No functional change.
Signed-off-by: Jason Kridner jkridner@gmail.com Signed-off-by: Dirk Behme dirk.behme@googlemail.com
---
* These two patches apply on top of last 3 pending OMAP3 patches:
http://lists.denx.de/pipermail/u-boot/2008-November/043771.html http://lists.denx.de/pipermail/u-boot/2008-November/043898.html http://lists.denx.de/pipermail/u-boot/2008-November/043899.html
* Compile tested for Beagle, Overo, Panora and EVM. Boot tested on Beagle.
cpu/arm_cortexa8/omap3/board.c | 73 ++++---- cpu/arm_cortexa8/omap3/clock.c | 263 ++++++++++++++++------------- include/asm-arm/arch-omap3/cpu.h | 351 +++++++++++++++++++++++++-------------- 3 files changed, 415 insertions(+), 272 deletions(-)
Index: u-boot-arm/include/asm-arm/arch-omap3/cpu.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/cpu.h +++ u-boot-arm/include/asm-arm/arch-omap3/cpu.h @@ -25,11 +25,20 @@ #ifndef _CPU_H #define _CPU_H
-#define OFFS(x) ((x) >> 2) - /* Register offsets of common modules */ /* Control */ +#ifndef __ASSEMBLY__ +typedef struct ctrl { + unsigned char res1[0xC0]; + unsigned short gpmc_nadv_ale; /* 0xC0 */ + unsigned short gpmc_noe; /* 0xC2 */ + unsigned short gpmc_nwe; /* 0xC4 */ + unsigned char res2[0x22A]; + unsigned int status; /* 0x2F0 */ +} ctrl_t; +#else /* __ASSEMBLY__ */ #define CONTROL_STATUS 0x2F0 +#endif /* __ASSEMBLY__ */
/* device type */ #define DEVICE_MASK (0x7 << 8) @@ -41,23 +50,54 @@
/* GPMC CS3/cs4/cs6 not avaliable */ #define GPMC_BASE (OMAP34XX_GPMC_BASE) - -#define GPMC_SYSCONFIG 0x10 -#define GPMC_IRQSTATUS 0x18 -#define GPMC_IRQENABLE 0x1C -#define GPMC_TIMEOUT_CONTROL 0x40 -#define GPMC_CONFIG 0x50 -#define GPMC_STATUS 0x54 #define GPMC_CONFIG_CS0 0x60 #define GPMC_CONFIG_CS6 0x150 - -#define GPMC_CONFIG_REG (GPMC_BASE + GPMC_CONFIG) #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) #define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6) #define GPMC_CONFIG_WP 0x10
#define GPMC_CONFIG_WIDTH 0x30
+#ifndef __ASSEMBLY__ +typedef struct gpmc { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned char res2[0x4]; + unsigned int irqstatus; /* 0x18 */ + unsigned int irqenable; /* 0x1C */ + unsigned char res3[0x20]; + unsigned int timeout_control; /* 0x40 */ + unsigned char res4[0xC]; + unsigned int config; /* 0x50 */ + unsigned int status; /* 0x54 */ + unsigned char res5[0x19C]; + unsigned int ecc_config; /* 0x1F4 */ + unsigned int ecc_control; /* 0x1F8 */ + unsigned int ecc_size_config; /* 0x1FC */ + unsigned int ecc1_result; /* 0x200 */ + unsigned int ecc2_result; /* 0x204 */ + unsigned int ecc3_result; /* 0x208 */ + unsigned int ecc4_result; /* 0x20C */ + unsigned int ecc5_result; /* 0x210 */ + unsigned int ecc6_result; /* 0x214 */ + unsigned int ecc7_result; /* 0x218 */ + unsigned int ecc8_result; /* 0x21C */ + unsigned int ecc9_result; /* 0x220 */ +} gpmc_t; + +typedef struct gpmc_csx { + unsigned int config1; /* 0x00 */ + unsigned int config2; /* 0x04 */ + unsigned int config3; /* 0x08 */ + unsigned int config4; /* 0x0C */ + unsigned int config5; /* 0x10 */ + unsigned int config6; /* 0x14 */ + unsigned int config7; /* 0x18 */ + unsigned int nand_cmd; /* 0x1C */ + unsigned int nand_adr; /* 0x20 */ + unsigned int nand_dat; /* 0x24 */ +} gpmc_csx_t; +#else /* __ASSEMBLY__ */ #define GPMC_CONFIG1 0x00 #define GPMC_CONFIG2 0x04 #define GPMC_CONFIG3 0x08 @@ -65,22 +105,7 @@ #define GPMC_CONFIG5 0x10 #define GPMC_CONFIG6 0x14 #define GPMC_CONFIG7 0x18 -#define GPMC_NAND_CMD 0x1C -#define GPMC_NAND_ADR 0x20 -#define GPMC_NAND_DAT 0x24 - -#define GPMC_ECC_CONFIG 0x1F4 -#define GPMC_ECC_CONTROL 0x1F8 -#define GPMC_ECC_SIZE_CONFIG 0x1FC -#define GPMC_ECC1_RESULT 0x200 -#define GPMC_ECC2_RESULT 0x204 -#define GPMC_ECC3_RESULT 0x208 -#define GPMC_ECC4_RESULT 0x20C -#define GPMC_ECC5_RESULT 0x210 -#define GPMC_ECC6_RESULT 0x214 -#define GPMC_ECC7_RESULT 0x218 -#define GPMC_ECC8_RESULT 0x21C -#define GPMC_ECC9_RESULT 0x220 +#endif /* __ASSEMBLY__ */
/* GPMC Mapping */ #define FLASH_BASE 0x10000000 /* NOR flash, */ @@ -95,35 +120,66 @@ #define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ #define ONENAND_MAP 0x20000000 /* OneNand addr */ /* (actual size small port) */ - /* SMS */ -#define SMS_SYSCONFIG 0x10 -#define SMS_RG_ATT0 0x48 -#define SMS_CLASS_ARB0 0xD0 +#ifndef __ASSEMBLY__ +typedef struct sms { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned char res2[0x34]; + unsigned int rg_att0; /* 0x48 */ + unsigned char res3[0x84]; + unsigned int class_arb0; /* 0xD0 */ +} sms_t; +#endif /* __ASSEMBLY__ */ + #define BURSTCOMPLETE_GROUP7 (0x1 << 31)
/* SDRC */ -#define SDRC_SYSCONFIG 0x10 -#define SDRC_STATUS 0x14 -#define SDRC_STATUS_REG (OMAP34XX_SDRC_BASE + SDRC_STATUS) -#define SDRC_CS_CFG 0x40 -#define SDRC_SHARING 0x44 -#define SDRC_DLLA_CTRL 0x60 -#define SDRC_DLLA_STATUS 0x64 -#define SDRC_DLLB_CTRL 0x68 -#define SDRC_DLLB_STATUS 0x6C +#ifndef __ASSEMBLY__ +typedef struct sdrc_cs { + unsigned int mcfg; /* 0x80 || 0xB0 */ + unsigned int mr; /* 0x84 || 0xB4 */ + unsigned char res1[0x4]; + unsigned int emr2; /* 0x8C || 0xBC */ + unsigned char res2[0x14]; + unsigned int rfr_ctrl; /* 0x84 || 0xD4 */ + unsigned int manual; /* 0xA8 || 0xD8 */ + unsigned char res3[0x4]; +} sdrc_cs_t; + +typedef struct sdrc_actim { + unsigned int ctrla; /* 0x9C || 0xC4 */ + unsigned int ctrlb; /* 0xA0 || 0xC8 */ +} sdrc_actim_t; + +typedef struct sdrc { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned int status; /* 0x14 */ + unsigned char res2[0x28]; + unsigned int cs_cfg; /* 0x40 */ + unsigned int sharing; /* 0x44 */ + unsigned char res3[0x18]; + unsigned int dlla_ctrl; /* 0x60 */ + unsigned int dlla_status; /* 0x64 */ + unsigned int dllb_ctrl; /* 0x68 */ + unsigned int dllb_status; /* 0x6C */ + unsigned int power; /* 0x70 */ + unsigned char res4[0xC]; + sdrc_cs_t cs[2]; /* 0x80 || 0xB0 */ +} sdrc_t; +#endif /* __ASSEMBLY__ */ + #define DLLPHASE_90 (0x1 << 1) #define LOADDLL (0x1 << 2) #define ENADLL (0x1 << 3) #define DLL_DELAY_MASK 0xFF00 #define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8))
-#define SDRC_POWER 0x70 #define PAGEPOLICY_HIGH (0x1 << 0) #define SRFRONRESET (0x1 << 7) #define WAKEUPPROC (0x1 << 26)
-#define SDRC_MCFG_0 0x80 #define DDR_SDRAM (0x1 << 0) #define DEEPPD (0x1 << 3) #define B32NOT16 (0x1 << 4) @@ -132,17 +188,12 @@ #define ADDRMUXLEGACY (0x1 << 19) #define CASWIDTH_10BITS (0x5 << 20) #define RASWIDTH_13BITS (0x2 << 24) -#define SDRC_MR_0 0x84 #define BURSTLENGTH4 (0x2 << 0) #define CASL3 (0x3 << 4) -#define SDRC_ACTIM_CTRLA_0 0x9C -#define SDRC_ACTIM_CTRLB_0 0xA0 -#define SDRC_ACTIM_CTRLA_1 0xC4 -#define SDRC_ACTIM_CTRLB_1 0xC8 -#define SDRC_RFR_CTRL 0xA4 +#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C) +#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4) #define ARE_ARCV_1 (0x1 << 0) #define ARCV (0x4e2 << 8) /* Autorefresh count */ -#define SDRC_MANUAL_0 0xA8 #define OMAP34XX_SDRC_CS0 0x80000000 #define OMAP34XX_SDRC_CS1 0xA0000000 #define CMD_NOP 0x0 @@ -158,79 +209,137 @@ #define REF_ON_IDLE (0x1 << 6)
/* timer regs offsets (32 bit regs) */ -#define TIDR 0x0 /* r */ -#define TIOCP_CFG 0x10 /* rw */ -#define TISTAT 0x14 /* r */ -#define TISR 0x18 /* rw */ -#define TIER 0x1C /* rw */ -#define TWER 0x20 /* rw */ -#define TCLR 0x24 /* rw */ -#define TCRR 0x28 /* rw */ -#define TLDR 0x2C /* rw */ -#define TTGR 0x30 /* rw */ -#define TWPS 0x34 /* r */ -#define TMAR 0x38 /* rw */ -#define TCAR1 0x3c /* r */ -#define TSICR 0x40 /* rw */ -#define TCAR2 0x44 /* r */ + +#ifndef __ASSEMBLY__ +typedef struct gptimer { + unsigned int tidr; /* 0x00 r */ + unsigned char res[0xc]; + unsigned int tiocp_cfg; /* 0x10 rw */ + unsigned int tistat; /* 0x14 r */ + unsigned int tisr; /* 0x18 rw */ + unsigned int tier; /* 0x1c rw */ + unsigned int twer; /* 0x20 rw */ + unsigned int tclr; /* 0x24 rw */ + unsigned int tcrr; /* 0x28 rw */ + unsigned int tldr; /* 0x2c rw */ + unsigned int ttgr; /* 0x30 rw */ + unsigned int twpc; /* 0x34 r*/ + unsigned int tmar; /* 0x38 rw*/ + unsigned int tcar1; /* 0x3c r */ + unsigned int tcicr; /* 0x40 rw */ + unsigned int tcar2; /* 0x44 r */ +} gptimer_t; +#endif /* __ASSEMBLY__ */ + /* enable sys_clk NO-prescale /1 */ #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
/* Watchdog */ -#define WWPS 0x34 /* r */ -#define WSPR 0x48 /* rw */ +#ifndef __ASSEMBLY__ +typedef struct watchdog { + unsigned char res1[0x34]; + unsigned int wwps; /* 0x34 r */ + unsigned char res2[0x10]; + unsigned int wspr; /* 0x48 rw */ +} watchdog_t; +#endif /* __ASSEMBLY__ */ + #define WD_UNLOCK1 0xAAAA #define WD_UNLOCK2 0x5555
/* PRCM */ #define PRCM_BASE 0x48004000 -#define CM_FCLKEN_IVA2 0x48004000 -#define CM_CLKEN_PLL_IVA2 0x48004004 -#define CM_IDLEST_PLL_IVA2 0x48004024 -#define CM_CLKSEL1_PLL_IVA2 0x48004040 -#define CM_CLKSEL2_PLL_IVA2 0x48004044 -#define CM_CLKEN_PLL_MPU 0x48004904 -#define CM_IDLEST_PLL_MPU 0x48004924 -#define CM_CLKSEL1_PLL_MPU 0x48004940 -#define CM_CLKSEL2_PLL_MPU 0x48004944 -#define CM_FCLKEN1_CORE 0x48004a00 -#define CM_ICLKEN1_CORE 0x48004a10 -#define CM_ICLKEN2_CORE 0x48004a14 + +#ifndef __ASSEMBLY__ +typedef struct prcm { + unsigned int fclken_iva2; /* 0x00 */ + unsigned int clken_pll_iva2; /* 0x04 */ + unsigned char res1[0x1c]; + unsigned int idlest_pll_iva2; /* 0x24 */ + unsigned char res2[0x18]; + unsigned int clksel1_pll_iva2 ; /* 0x40 */ + unsigned int clksel2_pll_iva2; /* 0x44 */ + unsigned char res3[0x8bc]; + unsigned int clken_pll_mpu; /* 0x904 */ + unsigned char res4[0x1c]; + unsigned int idlest_pll_mpu; /* 0x924 */ + unsigned char res5[0x18]; + unsigned int clksel1_pll_mpu; /* 0x940 */ + unsigned int clksel2_pll_mpu; /* 0x944 */ + unsigned char res6[0xb8]; + unsigned int fclken1_core; /* 0xa00 */ + unsigned char res7[0xc]; + unsigned int iclken1_core; /* 0xa10 */ + unsigned int iclken2_core; /* 0xa14 */ + unsigned char res8[0x28]; + unsigned int clksel_core; /* 0xa40 */ + unsigned char res9[0xbc]; + unsigned int fclken_gfx; /* 0xb00 */ + unsigned char res10[0xc]; + unsigned int iclken_gfx; /* 0xb10 */ + unsigned char res11[0x2c]; + unsigned int clksel_gfx; /* 0xb40 */ + unsigned char res12[0xbc]; + unsigned int fclken_wkup; /* 0xc00 */ + unsigned char res13[0xc]; + unsigned int iclken_wkup; /* 0xc10 */ + unsigned char res14[0xc]; + unsigned int idlest_wkup; /* 0xc20 */ + unsigned char res15[0x1c]; + unsigned int clksel_wkup; /* 0xc40 */ + unsigned char res16[0xbc]; + unsigned int clken_pll; /* 0xd00 */ + unsigned char res17[0x1c]; + unsigned int idlest_ckgen; /* 0xd20 */ + unsigned char res18[0x1c]; + unsigned int clksel1_pll; /* 0xd40 */ + unsigned int clksel2_pll; /* 0xd44 */ + unsigned int clksel3_pll; /* 0xd48 */ + unsigned char res19[0xb4]; + unsigned int fclken_dss; /* 0xe00 */ + unsigned char res20[0xc]; + unsigned int iclken_dss; /* 0xe10 */ + unsigned char res21[0x2c]; + unsigned int clksel_dss; /* 0xe40 */ + unsigned char res22[0xbc]; + unsigned int fclken_cam; /* 0xf00 */ + unsigned char res23[0xc]; + unsigned int iclken_cam; /* 0xf10 */ + unsigned char res24[0x2c]; + unsigned int clksel_cam; /* 0xf40 */ + unsigned char res25[0xbc]; + unsigned int fclken_per; /* 0x1000 */ + unsigned char res26[0xc]; + unsigned int iclken_per; /* 0x1010 */ + unsigned char res27[0x2c]; + unsigned int clksel_per; /* 0x1040 */ + unsigned char res28[0xfc]; + unsigned int clksel1_emu; /* 0x1140 */ +} prcm_t; +#else /* __ASSEMBLY__ */ #define CM_CLKSEL_CORE 0x48004a40 -#define CLKSEL_CORE 0xa40 -#define CM_FCLKEN_GFX 0x48004b00 -#define CM_ICLKEN_GFX 0x48004b10 #define CM_CLKSEL_GFX 0x48004b40 -#define CM_FCLKEN_WKUP 0x48004c00 -#define FCLKEN_WKUP 0xc00 -#define CM_ICLKEN_WKUP 0x48004c10 -#define ICLKEN_WKUP 0xc10 #define CM_CLKSEL_WKUP 0x48004c40 -#define CLKSEL_WKUP 0xc40 -#define CM_IDLEST_WKUP 0x48004c20 #define CM_CLKEN_PLL 0x48004d00 -#define CLKEN_PLL 0xd00 -#define CM_IDLEST_CKGEN 0x48004d20 #define CM_CLKSEL1_PLL 0x48004d40 -#define CLKSEL1_PLL 0xd40 -#define CM_CLKSEL2_PLL 0x48004d44 -#define CM_CLKSEL3_PLL 0x48004d48 -#define CM_FCLKEN_DSS 0x48004e00 -#define CM_ICLKEN_DSS 0x48004e10 -#define CM_CLKSEL_DSS 0x48004e40 -#define CM_FCLKEN_CAM 0x48004f00 -#define CM_ICLKEN_CAM 0x48004f10 -#define CM_CLKSEL_CAM 0x48004F40 -#define CM_FCLKEN_PER 0x48005000 -#define CM_ICLKEN_PER 0x48005010 -#define CM_CLKSEL_PER 0x48005040 #define CM_CLKSEL1_EMU 0x48005140 +#endif /* __ASSEMBLY__ */
#define PRM_BASE 0x48306000 -#define PRM_CLKSEL 0x48306d40 + +#ifndef __ASSEMBLY__ +typedef struct prm { + unsigned char res1[0xd40]; + unsigned int clksel; /* 0xd40 */ + unsigned char res2[0x50c]; + unsigned int rstctrl; /* 0x1250 */ + unsigned char res3[0x1c]; + unsigned int clksrc_ctrl; /* 0x1270 */ +} prm_t; +#else /* __ASSEMBLY__ */ #define PRM_RSTCTRL 0x48307250 -#define PRM_CLKSRC_CTRL 0x48307270 -#define CLKSRC_CTRL 0x1270 +#endif /* __ASSEMBLY__ */ + #define SYSCLKDIV_1 (0x1 << 6) #define SYSCLKDIV_2 (0x1 << 7)
@@ -259,26 +368,24 @@ #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) -#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
-#define RT_REQ_INFO_PERMISSION_1 0x68 -#define RT_READ_PERMISSION_0 0x50 -#define RT_WRITE_PERMISSION_0 0x58 -#define RT_ADDR_MATCH_1 0x60 - -#define GPMC_REQ_INFO_PERMISSION_0 0x48 -#define GPMC_READ_PERMISSION_0 0x50 -#define GPMC_WRITE_PERMISSION_0 0x58 - -#define OCM_REQ_INFO_PERMISSION_0 0x48 -#define OCM_READ_PERMISSION_0 0x50 -#define OCM_WRITE_PERMISSION_0 0x58 -#define OCM_ADDR_MATCH_2 0x80 - -#define IVA2_REQ_INFO_PERMISSION_0 0x48 -#define IVA2_READ_PERMISSION_0 0x50 -#define IVA2_WRITE_PERMISSION_0 0x58 +#ifndef __ASSEMBLY__ +typedef struct pm { + unsigned char res1[0x48]; + unsigned int req_info_permission_0; /* 0x48 */ + unsigned char res2[0x4]; + unsigned int read_permission_0; /* 0x50 */ + unsigned char res3[0x4]; + unsigned int wirte_permission_0; /* 0x58 */ + unsigned char res4[0x4]; + unsigned int addr_match_1; /* 0x58 */ + unsigned char res5[0x4]; + unsigned int req_info_permission_1; /* 0x68 */ + unsigned char res6[0x14]; + unsigned int addr_match_2; /* 0x80 */ +} pm_t; +#endif /*__ASSEMBLY__ */
/* Permission values for registers -Full fledged permissions to all */ #define UNLOCK_1 0xFFFFFFFF Index: u-boot-arm/cpu/arm_cortexa8/omap3/clock.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/clock.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/clock.c @@ -41,46 +41,46 @@ u32 get_osc_clk_speed(void) { u32 start, cstart, cend, cdiff, val; - u32 *prcm_base = (u32 *)PRCM_BASE; - u32 *prm_base = (u32 *)PRM_BASE; - u32 *gpt1_base = (u32 *)OMAP34XX_GPT1; - u32 *s32k_base = (u32 *)SYNC_32KTIMER_BASE; + prcm_t *prcm_base = (prcm_t *)PRCM_BASE; + prm_t *prm_base = (prm_t *)PRM_BASE; + gptimer_t *gpt1_base = (gptimer_t *)OMAP34XX_GPT1; + s32ktimer_t *s32k_base = (s32ktimer_t *)SYNC_32KTIMER_BASE;
- val = readl(prm_base + OFFS(CLKSRC_CTRL)); + val = readl(&prm_base->clksrc_ctrl);
/* If SYS_CLK is being divided by 2, remove for now */ val = (val & (~SYSCLKDIV_2)) | SYSCLKDIV_1; - writel(val, prm_base + OFFS(CLKSRC_CTRL)); + writel(val, &prm_base->clksrc_ctrl);
/* enable timer2 */ - val = readl(prcm_base + OFFS(CLKSEL_WKUP)) | CLKSEL_GPT1; + val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
/* select sys_clk for GPT1 */ - writel(val, prcm_base + OFFS(CLKSEL_WKUP)); + writel(val, &prcm_base->clksel_wkup);
/* Enable I and F Clocks for GPT1 */ - val = readl(prcm_base + OFFS(ICLKEN_WKUP)) | EN_GPT1 | EN_32KSYNC; - writel(val, prcm_base + OFFS(ICLKEN_WKUP)); - val = readl(prcm_base + OFFS(FCLKEN_WKUP)) | EN_GPT1; - writel(val, prcm_base + OFFS(FCLKEN_WKUP)); + val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC; + writel(val, &prcm_base->iclken_wkup); + val = readl(&prcm_base->fclken_wkup) | EN_GPT1; + writel(val, &prcm_base->fclken_wkup);
- writel(0, gpt1_base + OFFS(TLDR)); /* start counting at 0 */ - writel(GPT_EN, gpt1_base + OFFS(TCLR)); /* enable clock */ + writel(0, &gpt1_base->tldr); /* start counting at 0 */ + writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
/* enable 32kHz source, determine sys_clk via gauging */
/* start time in 20 cycles */ - start = 20 + readl(s32k_base + OFFS(S32K_CR)); + start = 20 + readl(&s32k_base->s32k_cr);
/* dead loop till start time */ - while (readl(s32k_base + OFFS(S32K_CR)) < start); + while (readl(&s32k_base->s32k_cr) < start);
/* get start sys_clk count */ - cstart = readl(gpt1_base + OFFS(TCRR)); + cstart = readl(&gpt1_base->tcrr);
/* wait for 40 cycles */ - while (readl(s32k_base + OFFS(S32K_CR)) < (start + 20)) ; - cend = readl(gpt1_base + OFFS(TCRR)); /* get end sys_clk count */ + while (readl(&s32k_base->s32k_cr) < (start + 20)) ; + cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ cdiff = cend - cstart; /* get elapsed ticks */
/* based on number of ticks assign speed */ @@ -133,11 +133,12 @@ void prcm_init(void) int xip_safe, p0, p1, p2, p3; u32 osc_clk = 0, sys_clkin_sel; u32 clk_index, sil_index; - u32 *prcm_base = (u32 *)PRCM_BASE; + prm_t *prm_base = (prm_t *)PRM_BASE; + prcm_t *prcm_base = (prcm_t *)PRCM_BASE; dpll_param *dpll_param_p;
f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start + - SRAM_VECT_CODE); + SRAM_VECT_CODE);
xip_safe = is_running_in_sram();
@@ -148,14 +149,17 @@ void prcm_init(void) osc_clk = get_osc_clk_speed(); get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
- sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ + /* set input crystal speed */ + sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
/* If the input clock is greater than 19.2M always divide/2 */ if (sys_clkin_sel > 2) { - sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */ + /* input clock divider */ + sr32(&prm_base->clksrc_ctrl, 6, 2, 2); clk_index = sys_clkin_sel / 2; } else { - sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */ + /* input clock divider */ + sr32(&prm_base->clksrc_ctrl, 6, 2, 1); clk_index = sys_clkin_sel; }
@@ -169,8 +173,8 @@ void prcm_init(void) sil_index = get_cpu_rev() - 1;
/* Unlock MPU DPLL (slows things down, and needed later) */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); - wait_on_value(ST_MPU_CLK, 0, CM_IDLEST_PLL_MPU, LDELAY); + sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY);
/* Getting the base address of Core DPLL param table */ dpll_param_p = (dpll_param *) get_core_dpll_param(); @@ -182,60 +186,78 @@ void prcm_init(void) * CORE DPLL * sr32(CM_CLKSEL2_EMU) set override to work when asleep */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); - wait_on_value(ST_CORE_CLK, 0, CM_IDLEST_CKGEN, LDELAY); + sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS); + wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, + LDELAY);
/* * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't * work. write another value and then default value. */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ - sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ - sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ - sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ - sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ - sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ - sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ - sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
- wait_on_value(ST_CORE_CLK, 1, CM_IDLEST_CKGEN, LDELAY); + /* m3x2 */ + sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2 + 1); + /* m3x2 */ + sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2); + /* Set M2 */ + sr32(&prcm_base->clksel1_pll, 27, 2, dpll_param_p->m2); + /* Set M */ + sr32(&prcm_base->clksel1_pll, 16, 11, dpll_param_p->m); + /* Set N */ + sr32(&prcm_base->clksel1_pll, 8, 7, dpll_param_p->n); + /* 96M Src */ + sr32(&prcm_base->clksel1_pll, 6, 1, 0); + /* ssi */ + sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV); + /* fsusb */ + sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV); + /* l4 */ + sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV); + /* l3 */ + sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV); + /* gfx */ + sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV); + /* reset mgr */ + sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM); + /* FREQSEL */ + sr32(&prcm_base->clken_pll, 4, 4, dpll_param_p->fsel); + /* lock mode */ + sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK); + + wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, + LDELAY); } else if (is_running_in_flash()) { /* * if running from flash, jump to small relocated code * area in SRAM. */ - p0 = readl(prcm_base + OFFS(CLKEN_PLL)); - sr32((u32) &p0, 0, 3, PLL_FAST_RELOCK_BYPASS); - sr32((u32) &p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - - p1 = readl(prcm_base + OFFS(CLKSEL1_PLL)); - sr32((u32) &p1, 27, 2, dpll_param_p->m2); /* Set M2 */ - sr32((u32) &p1, 16, 11, dpll_param_p->m); /* Set M */ - sr32((u32) &p1, 8, 7, dpll_param_p->n); /* Set N */ - sr32((u32) &p1, 6, 1, 0); /* set source for 96M */ - - p2 = readl(prcm_base + OFFS(CLKSEL_CORE)); - sr32((u32) &p2, 8, 4, CORE_SSI_DIV); /* ssi */ - sr32((u32) &p2, 4, 2, CORE_FUSB_DIV); /* fsusb */ - sr32((u32) &p2, 2, 2, CORE_L4_DIV); /* l4 */ - sr32((u32) &p2, 0, 2, CORE_L3_DIV); /* l3 */ + p0 = readl(&prcm_base->clken_pll); + sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); + sr32(&p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + + p1 = readl(&prcm_base->clksel1_pll); + sr32(&p1, 27, 2, dpll_param_p->m2); /* Set M2 */ + sr32(&p1, 16, 11, dpll_param_p->m); /* Set M */ + sr32(&p1, 8, 7, dpll_param_p->n); /* Set N */ + sr32(&p1, 6, 1, 0); /* set source for 96M */ + + p2 = readl(&prcm_base->clksel_core); + sr32(&p2, 8, 4, CORE_SSI_DIV); /* ssi */ + sr32(&p2, 4, 2, CORE_FUSB_DIV); /* fsusb */ + sr32(&p2, 2, 2, CORE_L4_DIV); /* l4 */ + sr32(&p2, 0, 2, CORE_L3_DIV); /* l3 */
- p3 = CM_IDLEST_CKGEN; + p3 = (u32)&prcm_base->idlest_ckgen;
(*f_lock_pll) (p0, p1, p2, p3); }
/* PER DPLL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); - wait_on_value(ST_PERIPH_CLK, 0, CM_IDLEST_CKGEN, LDELAY); + sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP); + wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
/* Getting the base address to PER DPLL param table */ + /* Set N */ dpll_param_p = (dpll_param *) get_per_dpll_param();
@@ -247,23 +269,23 @@ void prcm_init(void) * If using default divisors, write default divisor + 1 * and then the actual divisor value */ - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2 + 1); /* set M6 */ - sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2 + 1); /* set M5 */ - sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2 + 1); /* set M4 */ - sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2 + 1); /* set M3 */ - sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2 + 1); /* set M2 */ - sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ + sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2 + 1); /* set M6 */ + sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2); /* set M6 */ + sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2 + 1); /* set M5 */ + sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2); /* set M5 */ + sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2 + 1); /* set M4 */ + sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2); /* set M4 */ + sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2 + 1); /* set M3 */ + sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2); /* set M3 */ + sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2 + 1); /* set M2 */ + sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2); /* set M2 */ /* Workaround end */
- sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ - sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ - sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ - wait_on_value(ST_PERIPH_CLK, 2, CM_IDLEST_CKGEN, LDELAY); + sr32(&prcm_base->clksel2_pll, 8, 11, dpll_param_p->m); /* set m */ + sr32(&prcm_base->clksel2_pll, 0, 7, dpll_param_p->n); /* set n */ + sr32(&prcm_base->clken_pll, 20, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); /* lock mode */ + wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
/* Getting the base address to MPU DPLL param table */ dpll_param_p = (dpll_param *) get_mpu_dpll_param(); @@ -272,12 +294,18 @@ void prcm_init(void) dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
/* MPU DPLL (unlocked already) */ - sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ - sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ - sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ - sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(ST_MPU_CLK, 1, CM_IDLEST_PLL_MPU, LDELAY); + + /* Set M2 */ + sr32(&prcm_base->clksel2_pll_mpu, 0, 5, dpll_param_p->m2); + /* Set M */ + sr32(&prcm_base->clksel1_pll_mpu, 8, 11, dpll_param_p->m); + /* Set N */ + sr32(&prcm_base->clksel1_pll_mpu, 0, 7, dpll_param_p->n); + /* FREQSEL */ + sr32(&prcm_base->clken_pll_mpu, 4, 4, dpll_param_p->fsel); + /* lock mode */ + sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK); + wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY);
/* Getting the base address to IVA DPLL param table */ dpll_param_p = (dpll_param *) get_iva_dpll_param(); @@ -286,18 +314,23 @@ void prcm_init(void) dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
/* IVA DPLL (set to 12*20=240MHz) */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); - wait_on_value(ST_IVA2_CLK, 0, CM_IDLEST_PLL_IVA2, LDELAY); - sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ - sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ - sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ - sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ - sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ - wait_on_value(ST_IVA2_CLK, 1, CM_IDLEST_PLL_IVA2, LDELAY); + sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP); + wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY); + /* set M2 */ + sr32(&prcm_base->clksel2_pll_iva2, 0, 5, dpll_param_p->m2); + /* set M */ + sr32(&prcm_base->clksel1_pll_iva2, 8, 11, dpll_param_p->m); + /* set N */ + sr32(&prcm_base->clksel1_pll_iva2, 0, 7, dpll_param_p->n); + /* FREQSEL */ + sr32(&prcm_base->clken_pll_iva2, 4, 4, dpll_param_p->fsel); + /* lock mode */ + sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK); + wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
/* Set up GPTimers to sys_clk source only */ - sr32(CM_CLKSEL_PER, 0, 8, 0xff); - sr32(CM_CLKSEL_WKUP, 0, 1, 1); + sr32(&prcm_base->clksel_per, 0, 8, 0xff); + sr32(&prcm_base->clksel_wkup, 0, 1, 1);
sdelay(5000); } @@ -307,40 +340,42 @@ void prcm_init(void) *****************************************************************************/ void per_clocks_enable(void) { + prcm_t *prcm_base = (prcm_t *)PRCM_BASE; + /* Enable GP2 timer. */ - sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ - sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ - sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ + sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */ + sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */ + sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */
#ifdef CONFIG_SYS_NS16550 /* Enable UART1 clocks */ - sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); - sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); + sr32(&prcm_base->fclken1_core, 13, 1, 0x1); + sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
/* UART 3 Clocks */ - sr32(CM_FCLKEN_PER, 11, 1, 0x1); - sr32(CM_ICLKEN_PER, 11, 1, 0x1); + sr32(&prcm_base->fclken_per, 11, 1, 0x1); + sr32(&prcm_base->iclken_per, 11, 1, 0x1); #endif #ifdef CONFIG_DRIVER_OMAP34XX_I2C /* Turn on all 3 I2C clocks */ - sr32(CM_FCLKEN1_CORE, 15, 3, 0x7); - sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */ + sr32(&prcm_base->fclken1_core, 15, 3, 0x7); + sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */ #endif /* Enable the ICLK for 32K Sync Timer as its used in udelay */ - sr32(CM_ICLKEN_WKUP, 2, 1, 0x1); + sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
- sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON); - sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON); - sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON); - sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON); - sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON); - sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON); - sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON); - sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON); - sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON); - sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON); - sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON); - sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON); + sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON); + sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON); + sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON); + sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON); + sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON); + sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON); + sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON); + sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON); + sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON); + sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON); + sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON); + sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
sdelay(1000); } Index: u-boot-arm/cpu/arm_cortexa8/omap3/board.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/board.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/board.c @@ -56,34 +56,34 @@ static inline void delay(unsigned long l *****************************************************************************/ void secure_unlock_mem(void) { - u32 *pm_rt_ape_base = (u32 *)PM_RT_APE_BASE_ADDR_ARM; - u32 *pm_gpmc_base = (u32 *)PM_GPMC_BASE_ADDR_ARM; - u32 *pm_ocm_ram_base = (u32 *)PM_OCM_RAM_BASE_ADDR_ARM; - u32 *pm_iva2_base = (u32 *)PM_IVA2_BASE_ADDR_ARM; - u32 *sms_base = (u32 *)OMAP34XX_SMS_BASE; + pm_t *pm_rt_ape_base = (pm_t *)PM_RT_APE_BASE_ADDR_ARM; + pm_t *pm_gpmc_base = (pm_t *)PM_GPMC_BASE_ADDR_ARM; + pm_t *pm_ocm_ram_base = (pm_t *)PM_OCM_RAM_BASE_ADDR_ARM; + pm_t *pm_iva2_base = (pm_t *)PM_IVA2_BASE_ADDR_ARM; + sms_t *sms_base = (sms_t *)OMAP34XX_SMS_BASE;
/* Protection Module Register Target APE (PM_RT) */ - writel(UNLOCK_1, pm_rt_ape_base + OFFS(RT_REQ_INFO_PERMISSION_1)); - writel(UNLOCK_1, pm_rt_ape_base + OFFS(RT_READ_PERMISSION_0)); - writel(UNLOCK_1, pm_rt_ape_base + OFFS(RT_WRITE_PERMISSION_0)); - writel(UNLOCK_2, pm_rt_ape_base + OFFS(RT_ADDR_MATCH_1)); - - writel(UNLOCK_3, pm_gpmc_base + OFFS(GPMC_REQ_INFO_PERMISSION_0)); - writel(UNLOCK_3, pm_gpmc_base + OFFS(GPMC_READ_PERMISSION_0)); - writel(UNLOCK_3, pm_gpmc_base + OFFS(GPMC_WRITE_PERMISSION_0)); - - writel(UNLOCK_3, pm_ocm_ram_base + OFFS(OCM_REQ_INFO_PERMISSION_0)); - writel(UNLOCK_3, pm_ocm_ram_base + OFFS(OCM_READ_PERMISSION_0)); - writel(UNLOCK_3, pm_ocm_ram_base + OFFS(OCM_WRITE_PERMISSION_0)); - writel(UNLOCK_2, pm_ocm_ram_base + OFFS(OCM_ADDR_MATCH_2)); + writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1); + writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0); + writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0); + writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1); + + writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0); + writel(UNLOCK_3, &pm_gpmc_base->read_permission_0); + writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0); + + writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0); + writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0); + writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0); + writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
/* IVA Changes */ - writel(UNLOCK_3, pm_iva2_base + OFFS(IVA2_REQ_INFO_PERMISSION_0)); - writel(UNLOCK_3, pm_iva2_base + OFFS(IVA2_READ_PERMISSION_0)); - writel(UNLOCK_3, pm_iva2_base + OFFS(IVA2_WRITE_PERMISSION_0)); + writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0); + writel(UNLOCK_3, &pm_iva2_base->read_permission_0); + writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
/* SDRC region 0 public */ - writel(UNLOCK_1, sms_base + OFFS(SMS_RG_ATT0)); + writel(UNLOCK_1, &sms_base->rg_att0); }
/****************************************************************************** @@ -231,11 +231,11 @@ void s_init(void) * Routine: wait_for_command_complete * Description: Wait for posting to finish on watchdog *****************************************************************************/ -void wait_for_command_complete(unsigned int wd_base) +void wait_for_command_complete(watchdog_t *wd_base) { int pending = 1; do { - pending = readl(wd_base + WWPS); + pending = readl(&wd_base->wwps); } while (pending); }
@@ -245,7 +245,8 @@ void wait_for_command_complete(unsigned *****************************************************************************/ void watchdog_init(void) { - u32 *wd2_base = (u32 *)WD2_BASE; + watchdog_t *wd2_base = (watchdog_t *)WD2_BASE; + prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
/* * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is @@ -254,13 +255,13 @@ void watchdog_init(void) * should not be running and does not generate a PRCM reset. */
- sr32(CM_FCLKEN_WKUP, 5, 1, 1); - sr32(CM_ICLKEN_WKUP, 5, 1, 1); - wait_on_value(ST_WDT2, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ - - writel(WD_UNLOCK1, wd2_base + OFFS(WSPR)); - wait_for_command_complete(WD2_BASE); - writel(WD_UNLOCK2, wd2_base + OFFS(WSPR)); + sr32(&prcm_base->fclken_wkup, 5, 1, 1); + sr32(&prcm_base->iclken_wkup, 5, 1, 1); + wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5); + + writel(WD_UNLOCK1, &wd2_base->wspr); + wait_for_command_complete(wd2_base); + writel(WD_UNLOCK2, &wd2_base->wspr); }
/****************************************************************************** @@ -283,16 +284,16 @@ int dram_init(void) * memory on CS0. */ if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) { - do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); + do_sdrc_init(CS1, NOT_EARLY); make_cs1_contiguous(); }
- size0 = get_sdr_cs_size(SDRC_CS0_OSET); - size1 = get_sdr_cs_size(SDRC_CS1_OSET); + size0 = get_sdr_cs_size(CS0); + size1 = get_sdr_cs_size(CS1);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(1); + gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); gd->bd->bi_dram[1].size = size1;
return 0;