From: Quentin Schulz quentin.schulz@theobroma-systems.com
By default, the PX30 is configured for watchdog and tsadc to trigger a second global reset which is a more permissive reset than first global reset.
From TRM part 1 "2.3 System Reset Solution":
glb_srstn_1 will reset the all logic, and glb_srstn_2 will reset the all logic except GRF, SGRF and all GPIOs.
This enforces that the watchdog and tsadc trigger glb_srstn_1 as similarly done for RK3399 in U-Boot (in SDRAM driver for some reason?), TF-A and Coreboot.
Cc: Quentin Schulz foss+uboot@0leil.net Signed-off-by: Quentin Schulz quentin.schulz@theobroma-systems.com --- rockchip: px30: make watchdog and tsadc trigger a first global reset
Our devkits have a HW switch which electrically cuts the power and clock lines to the on-board eMMC so that the module is forced to boot from SD card (or enter USB flashing mode if none is present). This HW switch is electrically bypassed in SW by a GPIO in U-Boot SPL to allow for eMMC to be used in U-Boot and Linux.
In a second global reset, the GPIO do not get reset and is therefore still bypassing the HW switch, meaning the eMMC will be operational even though it is not desired (because the HW switch is supposed to enforce booting from SD card/USB when in that position).
This also mimics what's seen on RK3399.
To: Simon Glass sjg@chromium.org To: Philipp Tomsich philipp.tomsich@vrull.eu To: Kever Yang kever.yang@rock-chips.com Cc: u-boot@lists.denx.de --- Changes in v2: - add missing cru struct --- arch/arm/mach-rockchip/px30/px30.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 0641e6af0f..ded03ffa51 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -234,6 +234,7 @@ enum { int arch_cpu_init(void) { static struct px30_grf * const grf = (void *)GRF_BASE; + static struct px30_cru * const cru = (void *)CRU_BASE; u32 __maybe_unused val;
#ifdef CONFIG_SPL_BUILD @@ -285,6 +286,9 @@ int arch_cpu_init(void) /* Clear the force_jtag */ rk_clrreg(&grf->cpu_con[1], 1 << 7);
+ /* Make TSADC and WDT trigger a first global reset */ + clrsetbits_le32(&cru->glb_rst_con, 0x3, 0x3); + return 0; }
--- base-commit: 0cbeed4f6648e0e4966475e3544280a69ecb59d3 change-id: 20221111-px30-wdt-1-glb-rst-0ce41249727d
Best regards,